Fujitsu FR81S Manual Do Utilizador
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CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
251
7.1.5. Interrupts When Using Transmission FIFO and Flag
Setting Timing
When the transmission FIFO is used, an interrupt will generation when the storage data value of the
transmission FIFO is FTICR register (FTICR) setting value or less.
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When the storage data value of the transmission FIFO is FTICR register (FTICR) setting value or less.
the FIFO transmission data request bit (FCR1:FDRQ) will be set to "1". If FIFO transmission interrupt is
enabled (FCR1:FTIE=1) at this time, a transmission interrupt occurs.
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When required data is written to the transmission FIFO after the occurrence of a transmission interrupt,
write "0" to the FIFO transmission data request bit (FCR1:FDRQ) to clear the interrupt request.
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When the transmission FIFO is full, the FIFO transmission data request bit (FCR1:FDRQ) is set to "0".
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The presence of data in the transmission FIFO can be checked by reading the FIFO byte register
(FBYTE) or the transmission FIFO interrupt control register (FTICR).
When FBYTE=0x00, there is no data in the transmission FIFO.
Figure 7-5 Timing of Transmission Interrupts when Using Transmission FIFO
MB91520 Series
MN705-00010-1v0-E
1564