Fujitsu FR81S Manual Do Utilizador
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CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
264
7.2.4. Transmission Interrupts and Flag Setting Timing
A transmission interrupt occurs when the transmission data is transmitted from the transmission data
register (TDR) to the shift register for the transmission (SSR:TDRE=1) and then the transmission is started,
and when the transmission operation is not done.
Transmission Interrupts and Flag Setting Timing
Setting timing of transmission data empty flag (TDRE)
The timing is similar to those described in "7.1.4 Transmission Interrupt and Flag Setting Timing" in the
manual mode.
Setting timing of transmission bus idle flag (TBI)
When either of the following transmission operation is not done, the transmission bus idle flag bit
(SSR:TBI) is set to "1". At this time, if transmission bus idle interrupt is enabled (SCR:TBIE=1), the
transmission interrupt occurs.
⋅
The empty flag of the transmission data is set (TDRE=1) and transmission processing is not done.
⋅
In master operation (SCR:MS=0) in assist mode (LAMCR:LAMEN=1), the header transmission
processing is not done.
⋅
In assist mode (LAMCR:LAMEN=1), the response transmission processing is not done.
Moreover, the transmission bus idle flag bit (SSR:TBI) and the transmission interrupt request are cleared by
the following factors:
⋅
Transmission data is written in the transmission data register (TDR).
⋅
In master operation (SCR:MS=0) in assist mode (LAMCR:LAMEN=1), the header transmission is
being processed (LIN Break Field, Sync Field, ID Field).
⋅
In assist mode (LAMCR:LAMEN=1), the response transmission is being processed (data and
checksum).
MB91520 Series
MN705-00010-1v0-E
1577