Fujitsu FR81S Manual Do Utilizador
CHAPTER 45: FLASH MEMORY
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : FLASH MEMORY
FUJITSU SEMICONDUCTOR CONFIDENTIAL
33
5.3.2. Automatic Algorithm Execution State
This section explains the automatic algorithm execution state.
Because writing and erasing flash memory is performed by an automatic algorithm, the operating state can
be checked by the hardware sequence flag using the FRDY bit of the FLASH status register (FSTR) to
determine whether or not the automatic algorithm is executing.
Hardware Sequence Flag
This flag indicates the state of the automatic algorithm. When the FRDY bit of the FLASH status register
(FSTR) is "0", the operating state can be checked by reading from an arbitrary address in flash memory.
The following shows the bit configuration of the hardware sequence flag.
Figure 5-1 Bit Configuration of Hardware Sequence Flag
Notes:
⋅
It is impossible to read by word access. Always read using half-word or byte access in CPU programming
mode.
⋅
In CPU ROM mode, the hardware sequence flag cannot be read no matter which address is read.
When half-word access
bit15
Undefined
bit14
Undefined
bit13
Undefined
bit12
Undefined
bit11
Undefined
bit10
Undefined
bit9
Undefined
bit8
Undefined
bit7
DPOLL
bit6
TOGG1
bit5
TLOV
bit4
Undefined
bit3
SETI
bit2
TOGG2
bit1
Undefined
bit0
Undefined
bit7
DPOLL
bit6
TOGG1
bit5
TLOV
bit4
Undefined
bit3
SETI
bit2
TOGG2
bit1
Undefined
bit0
Undefined
When byte access
MB91520 Series
MN705-00010-1v0-E
1954