Fujitsu FR81S Manual Do Utilizador
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CHAPTER 7: RESET
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
21
5.2.3. Watchdog Reset 0
The watchdog reset 0 is shown.
It is a hardware reset input from the FR81S-core built-in watchdog timer 0 (software watchdog).
Resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. Whether
or not an irregular reset has been detected, an initialize reset (INIT) will be issued.
MB91520 Series
MN705-00010-1v0-E
274