Fujitsu FR81S Manual Do Utilizador
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
4.2. DMA Request Clear Register 1 : ICSEL1 (Interrupt
Clear SELect register 1)
The bit configuration of DMA request clear register 1 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #17).
ICSEL1: Address 0401
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
EISEL[2:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX R0,WX R0,WX R0,WX R0,WX
R/W
R/W
R/W
[bit2 to bit0] EISEL[2:0] (External Interrupt request SELection) : Interrupt clear selection bits for
external interrupts 8 to 15
EISEL[2:0]
Clear target
000
External interrupt 8
001
External interrupt 9
010
External interrupt 10
011
External interrupt 11
100
External interrupt 12
101
External interrupt 13
110
External interrupt 14
111
External interrupt 15
MB91520 Series
MN705-00010-1v0-E
356