Fujitsu FR81S Manual Do Utilizador
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CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
17
4.8. DMA Request Clear Register 8 : ICSEL8 (Interrupt
Clear SELect register 8)
The bit configuration of DMA request clear register 8 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #42).
ICSEL8: Address 0408
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PPGSEL2[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
R/W
R/W
[bit1, bit0] PPGSEL2[1:0] (PPG SELection2) : Interrupt clear selection bits for PPG4, 5, 14, 15
PPGSEL2[1:0]
Clear target
00
PPG4
01
PPG5
10
PPG14
11
PPG15
MB91520 Series
MN705-00010-1v0-E
362