Fujitsu FR81S Manual Do Utilizador
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CHAPTER 18: WATCHDOG TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WATCHDOG TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
4.2. Watchdog Timer 0 Clear Register : WDTCPR0
(WatchDog Timer Clear Pattern Register 0)
The bit configuration of the watchdog timer 0 clear register is shown.
This register activates or clears (delays issue of a reset signal) the watchdog timer 0.
WDTCPR0 : Address 003D
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
CPAT[7:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
R0,W
[bit7 to bit0] CPAT[7:0] (Clear PATtern) : Watchdog Timer 0 clear
The watchdog timer 0 is activated by the first write to this register after the reset is released. The watchdog
timer is cleared after being activated by writing a value with all of the bits inverted from the previously
written value. If a value other than the inverse value of the previously written value is written, the watchdog
reset 0 is issued at that time.
The value read out from this register is always "0x00" regardless of the value written.
MB91520 Series
MN705-00010-1v0-E
620