Fujitsu FR81S Manual Do Utilizador
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CHAPTER 20: RELOAD TIMER
6. Application Note
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RELOAD TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
64
6.4. PWM
PWM is shown below.
PWM is the feature which generates an output pulse by configuring the pulse interval and H width.
An activation trigger launches a load from TMRLRA to the counter and executes a down count.
TOUT outputs the "L level" after an activation trigger and then outputs the "H level" when the counter
value becomes smaller than the TMRLRB value. When an underflow occurs, TOUT output returns to its
initial value. (When OUTL=0)
value becomes smaller than the TMRLRB value. When an underflow occurs, TOUT output returns to its
initial value. (When OUTL=0)
When RELD=0, "Activation trigger=> TMRLRA load => Down count => Underflow, then counter stops
the down count.
the down count.
When RELD=1, Counter is loaded with TMRLRA, and it is decremented for each load whenever an
underflow occurs, such as Activation trigger=> TMRLRA load=> Down count=> Underflow=> TMRLRA
load=> Down count, and so on.
underflow occurs, such as Activation trigger=> TMRLRA load=> Down count=> Underflow=> TMRLRA
load=> Down count, and so on.
[Configuration] To use the timer as PWM, configure as follows.
1. When TIN input is not used
TMCSR
TMRLRA TMRLRB
MOD
[1:0]
TRGM
[1:0]
CSL
[2:0]
GATE EF OUTL RELD INTE UF CNTE TRG
(A)
(B)
10
0
*1
0
-
*2
*3
*4
-
1
S
(A): The count initial value when activation trigger occurs/The reload value at an underflow (when
RELD=1)
(B): Set the value to compare to the counter value (TMRLRB < TMRLRA) *5
S :Use at timer activation
-:Does not influence operation
*1:Count clock division setting
RELD=1)
(B): Set the value to compare to the counter value (TMRLRB < TMRLRA) *5
S :Use at timer activation
-:Does not influence operation
*1:Count clock division setting
CSL[2:0]= 000------Division of peripheral clock (PCLK) by 2
CSL[2:0]= 010------Division of peripheral clock (PCLK) by 8
CSL[2:0]= 011------Division of peripheral clock (PCLK) by 16
CSL[2:0]= 100------Division of peripheral clock (PCLK) by 32
CSL[2:0]= 101------Division of peripheral clock (PCLK) by 64
*2:TOUT output polarity setting
OUTL= 0------Initial value L=> Count L from TMRLRA => H, the counter value is smaller than
TMRLRB
OUTL= 1------Initial value H=> Count H from TMRLRA => L, the counter value is smaller than
TMRLRB
*3:Reload setting when an underflow occurs
*3:Reload setting when an underflow occurs
RELD= 0------One-shot mode
RELD= 1------Reload mode
*4:Interrupt request enable setting
INTE= 0------Interrupt disabled
INTE= 1------Interrupt enabled
*5:To use TOUT output with L clip output, set to TMRLRB = 0.
To use TOUT output with H clip output, set to TMRLRB = "TMRLRA + 1".
To use TOUT output with H clip output, set to TMRLRB = "TMRLRA + 1".
MB91520 Series
MN705-00010-1v0-E
791