Fujitsu FR81S Manual Do Utilizador
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CHAPTER 21: 32-BIT FREE-RUN TIMER
9. Notes
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
43
9. Notes
This section explains notes of the free-run timer.
Clear Timing of the Free-run Timer
⋅
When a reset is performed (RSTX pin input, watchdog reset, software reset, etc.) , the counter will stop
counting after initializing to "0000_0000
H
".
⋅
A software clear (TCCSH:SCLR=1) clears the counter as soon as the clear request is generated.
However, in the case of compare match, the counter is cleared in the same timing as the counting up.
⋅
Counter clear operation (software, compare match) will only be enabled while the free-run timer is in
operation. To clear the counter while the free-run timer is in stop, you need to write "0000_0000
H
" to the
timer count data register.
Writing to the timer data register
⋅
Always write a value to the free-run timer while the free-run timer is inactive (STOP = "1"), using a
word access instruction.
External clock operation
⋅
The timings of the compare match output and generation of interrupt of the external clock will be the
next count clock timing after the compare match. Therefore, in order to the generate compare match
output and interrupt, 1 clock (external clock) must at least be input after the compare match.
Read-modify-write
⋅
Compare clear interrupt flag bits of the timer control register are "1" when read using a read-modify-write
instruction.
MB91520 Series
MN705-00010-1v0-E
838