Fujitsu FR81S Manual Do Utilizador
CHAPTER 22: 32-BIT OUTPUT COMPARE
7. Q&A
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
30
7.8. Interrupt Related Register?
This section shows the interrupt related register.
Both the output compare interrupt vector and the output compare interrupt level are set.
The relation among the output compare channel, interrupt level, and interrupt vector is shown in the table
below:
For the interrupt level and interrupt vector, see "CAHPTER: INTERRUPT CONTROL (INTERRUPT
CONTROLLER)".
Channel
Interrupt Vector (Default)
Interrupt Level Setting Bit (ICR[4:0])
Output compare
6/7
#58
Address: 0FFF14
H
Interrupt level register (ICR42)
Address: 0046A
H
Output compare
8 to 10
#59
Address: 0FFF10
H
Interrupt level register (ICR43)
Address: 0046B
H
The interrupt request flag (OCSLxy.IOPx, OCSLxy.IOPy x=6,8,10 y=7,9,11) are not cleared automatically.
Before recovering from the interrupt process, write "0" to each bit to clear with software.
MB91520 Series
MN705-00010-1v0-E
867