Intel 253668-032US Manual Do Utilizador

Vol. 3 15-1

CHAPTER 15

MACHINE-CHECK ARCHITECTURE

This chapter describes the machine-check architecture and machine-check

exception mechanism found in the Pentium 4, Intel Xeon, and P6 family

(#MC),” for more information on machine-check exceptions. A brief descrip-

tion of the Pentium processor’s machine check capability is also given.
Additionally, a signaling mechanism for software to respond to hardware

corrected machine check error is covered.

15.1 MACHINE-CHECK

ARCHITECTURE

The Pentium 4, Intel Xeon, and P6 family processors implement a machine-

check architecture that provides a mechanism for detecting and reporting

hardware (machine) errors, such as: system bus errors, ECC errors, parity

errors, cache errors, and TLB errors. It consists of a set of model-specific

registers (MSRs) that are used to set up machine checking and additional

banks of MSRs used for recording errors that are detected.
The processor signals the detection of an uncorrected machine-check error

by generating a machine-check exception (#MC), which is an abort class

exception. The implementation of the machine-check architecture does not

ordinarily permit the processor to be restarted reliably after generating a

machine-check exception. However, the machine-check-exception handler

can collect information about the machine-check error from the machine-

check MSRs.
Starting with 45nm Intel 64 processor with CPUID signature

DisplayFamily_DisplayModel encoding of 06H_1AH (see CPUID instruction in

report information on corrected machine-check errors and deliver a

programmable interrupt for software to respond to MC errors, referred to as

corrected machine-check error interrupt (CMCI). See Section 15.5 for detail.
Intel 64 processors supporting machine-check architecture and CMCI may

also support an additional enhancement, namely, support for software

recovery from certain uncorrected recoverable machine check errors. See