Intel 253668-032US Manual Do Utilizador
15-26 Vol. 3
MACHINE-CHECK ARCHITECTURE
IA32_MCi_STATUS register. Recovery actions for SRAO errors are MCA error code
specific. The MISCV and the ADDRV flags in the IA32_MCi_STATUS register are
set when the additional error information is available from the IA32_MCi_MISC
and the IA32_MCi_ADDR registers. System software needs to inspect the MCA
error code fields in the IA32_MCi_STATUS register to identify the specific
recovery action for a given SRAO error. If MISCV and ADDRV are not set, it is
recommended that no system software error recovery be performed however,
you can resume execution.
specific. The MISCV and the ADDRV flags in the IA32_MCi_STATUS register are
set when the additional error information is available from the IA32_MCi_MISC
and the IA32_MCi_ADDR registers. System software needs to inspect the MCA
error code fields in the IA32_MCi_STATUS register to identify the specific
recovery action for a given SRAO error. If MISCV and ADDRV are not set, it is
recommended that no system software error recovery be performed however,
you can resume execution.
•
software recoverable action required (SRAR) - a UCR error that requires system
software to take a recovery action on this processor before scheduling another
stream of execution on this processor. SRAR errors indicate that the error was
detected and raised at the point of the consumption in the execution flow. An
SRAR error is indicated with UC=1, PCC=0, S=1, EN=1 and AR=1 in the
IA32_MCi_STATUS register. Recovery actions are MCA error code specific. The
MISCV and the ADDRV flags in the IA32_MCi_STATUS register are set when the
additional error information is available from the IA32_MCi_MISC and the
IA32_MCi_ADDR registers. System software needs to inspect the MCA error code
fields in the IA32_MCi_STATUS register to identify the specific recovery action for
a given SRAR error. If MISCV and ADDRV are not set, it is recommended that
system software shutdown the system.
software to take a recovery action on this processor before scheduling another
stream of execution on this processor. SRAR errors indicate that the error was
detected and raised at the point of the consumption in the execution flow. An
SRAR error is indicated with UC=1, PCC=0, S=1, EN=1 and AR=1 in the
IA32_MCi_STATUS register. Recovery actions are MCA error code specific. The
MISCV and the ADDRV flags in the IA32_MCi_STATUS register are set when the
additional error information is available from the IA32_MCi_MISC and the
IA32_MCi_ADDR registers. System software needs to inspect the MCA error code
fields in the IA32_MCi_STATUS register to identify the specific recovery action for
a given SRAR error. If MISCV and ADDRV are not set, it is recommended that
system software shutdown the system.
Table 15-6 summarizes UCR, corrected, and uncorrected errors.
Table 15-6. MC Error Classifications
Type of Error
1
NOTES:
1. VAL=1, EN=1 for UC=1 errors; OVER=0 for UC=1 and PCC=0 errors SRAR, SRAO and UCNA errors
are supported by the processor only when IA32_MCG_CAP[24] (MCG_SER_P) is set.
UC PCC S AR Signaling Software Action
Example
Uncorrected Error
(UC)
1
1
x x
MCE
Reset the system
SRAR
1
0
1 1
MCE
For known MCACOD, take
specific recovery action;
For unknown MCACOD,
For unknown MCACOD,
must bugcheck
Cache to
processor load
error
SRAO
1
0
1 0
MCE
For known MCACOD, take
specific recovery action;
For unknown MCACOD,
For unknown MCACOD,
OK to keep the system
running
Patrol scrub and
explicit writeback
poison errors
UCNA
1
0
0 0
CMC
Log the error and Ok to
keep the system running
Poison detection
error
Corrected Error (CE) 0
0
x x
CMC
Log the error and no
corrective action
required
ECC in caches and
memory