Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Ficha De Dados

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the
corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. 

The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in
level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. 

The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in
positive edge-triggered or negative edge-triggered modes.

Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers;
AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of
registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the AIC_IMR register. A
disabled interrupt does not affect servicing of other interrupts.

All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared
by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in level-
sensitive mode has no effect.

The clear operation is perfunctory, as the software must perform an action to reinitialize the “memorization” circuitry
activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test
or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt.

The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only
the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (

) The automatic clear reduces the operations required by the interrupt service routine entry code

to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing
feature enabled as it is considered uniquely as a FIQ source. (For further details, 

The automatic clear of the interrupt source 0 is performed when AIC_FVR is read. 

For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR
(Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not.

The AIC_ISR register reads the number of the current interrupt (see 

) and the register

AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. 

Each status referred to above can be used to optimize the interrupt handling of the systems.