Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Ficha De Dados
Códigos do produto
AT91SAM9N12-EK
620
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
36.7
Functional Description
36.7.1 Modes
of
Operation
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3
are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line
driven as an output by the transmitter.
are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line
driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the
MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The
NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven
and can be used for other purposes.
MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The
NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven
and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only
in Master Mode.
in Master Mode.
36.7.2 Data
Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL
bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine
the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states,
resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master
must reconfigure itself each time it needs to communicate with a different slave.
bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine
the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states,
resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master
must reconfigure itself each time it needs to communicate with a different slave.
shows the four modes and corresponding parameter settings.
and
show examples of data transfers.
Table 36-4. SPI Bus Protocol Mode
SPI Mode
CPOL
NCPHA
Shift SPCK Edge
Capture SPCK Edge
SPCK Inactive Level
0
0
1
Falling
Rising
Low
1
0
0
Rising
Falling
Low
2
1
1
Rising
Falling
High
3
1
0
Falling
Rising
High