Intel E3815 FH8065301567411 Ficha De Dados
Códigos do produto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1865
16.9.3
Revision ID and Class Code Register (REVCLASSCODE)—Offset
8h
Access Method
Default: 00000000h
16.9.4
Cache Line Size, Latency Timer, and Header Type Register
(CLLATHEADERBIST)—Offset Ch
Access Method
Default: 00000000h
8
0h
RW
SERR# Enable (SERR_ENABLE):
This bit controls the sending of DO_SERR messages
on IOSF SB.
7:3
00h
RO
Reserved5:
Reserved.
2
0h
RW
Bus Master Enable (BME):
If this bit is 0, Bridge does not generate any new upstream
transaction on IOSF as a master. Reset value of this bit is 0.
1
0h
RW
Memory Space Enable (MSE):
This bit controls Bridges response to downstream
memory accesses. When set, accesses to the memory space of the device are enabled.
Reset value of this bit is 0.
0
0h
RO
Reserved6:
Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CLAS
S
_
CO
D
E
S
RID
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
000000h
RO
Class Code (CLASS_CODES):
This register is read-only and is used to identify the
generic function of the device and, in some cases, a specific register level programming
interface. The register is broken into three byte size fields. The upper byte (at offset
0Bh) is a base class code which broadly classifies the type of function the device
performs. The middle byte (at offset 0Ah) is a sub-class code which identifies more
specifically the function of the device. The lower byte (at offset 09h) identifies a specific
register-level programming interface (if any) so that device independent software can
interact with the device. This register is tied to a strap at the top level.
7:0
00h
RO
Revision ID (RID):
Identifies the revision of a particular AHB device. This is tied to a
strap at the top level.
Type:
PCI Configuration Register
(Size: 32 bits)
Offset: