Intel E3815 FH8065301567411 Ficha De Dados
Códigos do produto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2090
Datasheet
17.19.21 PCS_DWORD20 (pcs_dword20)—Offset 50h
Access Method
Default: 80808080h
17
0h
RW
cal_inv:
Calibration Feedback Invert Inverse the logic of counter increment decrement
depends on the FB
16
0h
RW
cal_rst:
Calibration Reset Reset state machine
15:14
1h
RW
calclkdivsel_1_0:
Calibration Clock Divider Select 00 - div2 of CRICLK 01 - div4 of
CRICLK 10 - div8 of CRICLK 11 - div16 of CRICLK Note: Calibration clock period target
is 160nS
13
0h
RO
reserved525:
reserved
12
0h
RO
calib_done:
Calibration Completion Indicator
11:8
Fh
RW
cal_fb_count:
Calibration Cycle Count Limit per target Each calibration target is
clocked for 16 * cal_fb_count clock cycles. Max is 240 clock cycles (default)
7:6
0h
RW
adc_acctime_1_0:
ADC Accumulation Time Select This selects the conversion time for
the Analog to Digital Converter. ADC clock frequency is set by bits [5:4] in this register.
00: 1024 ADC clocks (default) 01: 512 ADC clocks 10: 256 ADC clocks 11: Infinite
(ADC in continuous accumulation) Note: If LRC mode and set to '11', then adctime =
1024cycles.
5:4
1h
RW
adc_clksel_1_0:
ADC Clock Frequency Select This selects the input clock frequency to
the Analog to Digital Converter. 00: CRI clock div2 01: CRI clock div1 10: CRI clock div4
11: CRI clock div8 NOTE: Target is 50Mhz.
3:1
0h
RW
adcmuxsel_2_0:
ADC Analog Mux Select This selects the analog voltage input to the
Analog to Digital Converter. 000: Vss 001: Vcc 010: LRC R1 voltage divider 011: LRC
sense net 100: input from Tx 101: input from Rx (or Tx #2) 110: input from Clock 111:
input from reference generator Note: Mux select is controlled by the FSM during LRC.
0
0h
RW
adcstart:
ADC start This bit resets the ADC counter and starts a new acquisition. This
bit should remain 1'b1 while the ADC is active and acquiring data. 0: Disable ADC logic
and analog circuitry 1: Enable ADC and start A2D conversion.
Bit
Range
Default &
Access
Description
Type:
Message Bus Register
(Size: 32 bits)
pcs_dword20:
Op Codes:
0h - Read, 1h - Write
0h - Read, 1h - Write
31
28
24
20
16
12
8
4
0
1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
rxvgarc
code
_7_0
rx
te
rm
rc
code
_7_0
txrc
code
_7_0
ir
ef
rc
code
_7_0