Intel E3815 FH8065301567411 Ficha De Dados

Intel

®

 Atom™ Processor E3800 Product Family

2488

Datasheet

Default: 00000000h

1

0h

RW

Port Enabled/Disabled (PED) RW1CS. Default = 0. 1 = Enabled. 0 = Disabled. 

Ports may only be enabled by the xHC. Software cannot enable a port by writing a 1 to 

this flag. A port may be disabled by software writing a 1 to this flag. This flag shall 

automatically be cleared to 0 by a disconnect event or other fault condition. Note that 

the bit status does not change until the port state actually changes. There may be a 

delay in disabling or enabling a port due to other host controller or bus events. When 

the port is disabled (PED = 0) downstream propagation of data is blocked on this port, 

except for reset. For USB2 protocol ports: When the port is in the Disabled state, 

software shall reset the port (PR = 1) to transition PED to 1 and the port to the Enabled 

state. For USB3 protocol ports: When the port is in the Polling state (after detecting an 

attach), the port shall automatically transition to the Enabled state and set PED to 1 

upon the completion of successful link training. When the port is in the Disabled state, 

software shall write a 5 (RxDetect) to the PLS field to transition the port to the 

Disconnected state. Refer to section 4.19.1.2. of xhci specification. PED shall 

automatically be cleared to 0 when PR is set to 1, and set to 1 when PR transitions from 

1 to 0 after a successful reset. Refer to Port Reset (PR) bit for more information on how 

the PED bit is managed. Note that when software writes this bit to a 1, it shall also write 

a 0 to the PR bit. This flag is 0 if PP is 0.

0

0h

RW

Current Connect Status (CCS) ROS. Default = 0. 1 = A device is connected to the 

port. 0 = A device is not connected. This value reflects the current state of the port, and 

may not correspond directly to the event that caused the Connect Status Change (CSC) 

bit to be set to 1. Refer to sections 4.19.3 and 4.19.4 for more details on the Connect 

Status Change (CSC) assertion conditions. This flag is 0 if PP is 0.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:22, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD

26

FLA

U2_TIMEOUT

U1_TIMEOUT

31:17

0h

RO

reserved

16

0h

RW

Reg field FLA

15:8

0h

RW

Reg field U2_TIMEOUT

7:0

0h

RW

Reg field U1_TIMEOUT