Intel E3815 FH8065301567411 Ficha De Dados
Códigos do produto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2847
Default: 0000000000000000h
21.11.11 reg_ISRLPESC_type (ISRLPESC)—Offset 50h
ISRLPESC
Access Method
Default: 0000000000000000h
Type:
Memory Mapped I/O Register
(Size: 64 bits)
ISRSC:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD
0
W
ak
e_S
CU
_S
ta
tu
s
Go
S0
ixI
n
t_
SC
U_
Stat
us
RS
VD
1
LP
E_S
C
_I
PC
_
R
eq
ue
st
_
S
ta
tu
s
LP
E_
S
C
_I
PC
_
D
on
e_S
ta
tu
s
Bit
Range
Default &
Access
Description
63:34
0b
RO
RSVD0:
Reserved
33
0b
RW/1C
Wake_SCU_Status:
This bit is set by hardware when a blocked transaction is detected.
It generates a wake to the SCU
32
0b
RW/1C
GoS0ixInt_SCU_Status:
This bit is set by expiry of the Re-entry timer. The bit gets set
only if GoS0ixInt_En bit is set and this interrupt is unmasked.
31:2
0b
RO
RSVD1:
Reserved
1
0b
RO
LPE_SC_IPC_Request_Status:
IPCLPESC Interrupt Request 1: interrupt when LPE
writes a message into IPCLPESC register with bit 63 set 0: Deasserted
0
0b
RW/1C
LPE_SC_IPC_Done_Status:
IPCSC Interrupt Request 1: interrupt when LPE writes a
message into IPCSC register with bit 62 set is asserted 0: Deasserted.
Type:
Memory Mapped I/O Register
(Size: 64 bits)
ISRLPESC:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h