Intel E3815 FH8065301567411 Ficha De Dados

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

425

I/O Base Address. This is used only by SBIOS. This register is the base address for the 

MMIO_INDEX and MMIO_DATA registers SOXi Context Save/Restore : Yes NOTE : This 

was at 14h for CDV. This register provides the Base offset of the I/O registers within 

Device #2. Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable 

(PCICMD bit 0) set. Access is disallowed : 1)in PM states D1-D3 or 2)if IO Enable is 

clear or 3)if Device #2 is turned off or 4)if Internal graphics is disabled thru the fuse or 

fuse override mechanisms. Note that access to this IO BAR is independent of VGA 

functionality within Device #2. If accesses to this IO bar is allowed then the GMCH 

claims all 8, 16 or 32 bit IO cycles from the CPU that falls within the 8B claimed.

Default: 00000001h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD

_0

MBA_1

31:4

0000000h

RO

Memory Base Address (MBA2): Set by the OS, these bits correspond 

to address signals [63:36].

3:0

0h

RO

Memory Base Address (MBA)Set by the OS, these bits correspond to 

address signals [35:32]

PCI Configuration Register

(Size: 32 bits)

Core

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

RS

VD_0

B

A

SE_AD

D

RES

S

_1

RS

VD_2

RESO

URC

E

_

T

YP

E_R

T

E_3

31:16

0000h

RO

Reserved

15:3

0000h

RW

BA: Set by the OS, these bits correspond to 

address signals [15:6].IOBAR is to be used for both GTLC register programming and 

GTT table programming. This is an indirect access method.

2:1

00b

RO

Reserved