Intel E3815 FH8065301567411 Ficha De Dados

Intel

®

 Atom™ Processor E3800 Product Family

608

Datasheet

Pipe A CRC Color Channel Result Register

Default: 00000000h

Pipe A Panel Self Refresh Control

31:23

0b

RW

Write as zero

22:0

0b

RW

Expected CRC Value for Color Channel. This is the value used 

to generate the CRC error status and interrupt. Resultant CRC values are compared to 

this register after the completion of a CRC calculation. Status indications are in the 

PIPEASTAT register.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RE

SERV

ED

CO

LOR_C

H

A

NNE

L_CRC_RE

S

U

LT

_V

A

LUE

31:23

0b

RO

Read only

22:0

0b

RO

This field contains the resultant CRC value 

for the particular Color Channel at the end of a frame. A status bit can be used as an 

indication that the data is the valid result of a CRC calculation.