Intel E3815 FH8065301567411 Ficha De Dados
Códigos do produto
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
918
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIPE_B_UNDERFL
OW_ST
A
TUS
SPRITE
_
D
_FLIP
_
D
O
NE_INTE
RRU
PT_E
NABLE
CRC_ERROR_E
N
ABLE
CRC_D
O
NE
_ENA
BLE
PE
R
FO
R
MA
NCE
_
CO
UNTE
R
2_INTE
RRU
PT_E
NABLE
PLANE_B_FLIP
_DONE_INTERRU
PT_ENABLE
VER
T
ICAL_SYN
C_INTERRU
PT_ENABLE
D
ISPLA
Y_LINE_COMP
A
RE_E
NABLE
B
LM
_
EV
E
N
T
_
ENA
B
LE
SP
RIT
E
_C_FLIP
_
D
O
NE_INTE
RRU
PT_E
NABLE
ODD_FIE
LD_INTERR
UPT_E
V
ENT_E
N
ABLE
E
V
E
N
_FIE
LD_INTERR
U
PT_E
VENT_E
NABLE
PA
NE
L_SEL
F_
R
E
FRESH_PSR_INTE
RRU
PT_E
NABLE
_
ON_P
IPE_B
S
TAR
T_OF_VE
R
TICAL
_
B
LANK_INTE
RRUPT_E
NABLE
PIPE
_B_FRAM
E
S
TA
R
T_INTERRU
PT_ENA
BLE
PI
PE_B_H
O
R
IZ
O
N
TA
L_
BLA
N
K_INTERRU
PT_ENA
BLE
SPRITE
_D_FLIP_DONE_INTE
RRUP
T
_ST
A
TUS
SPRITE_C_FLIP_DONE_INTE
RRUP
T
_ST
A
TUS
CRC_ERRO
R_ST
A
T
US
CRC_D
O
NE
_INTERRUP
T
_S
TA
TUS
SE
C
O
N
D
_P
E
R
FORMANCE_COUNTER2_INTE
RRUP
T
_ST
A
TUS
PL
A
N
E_B_FLIP
_DONE_INTE
RRUPT
_ST
A
TUS
PIPE_B_VE
R
TICAL_SYNC_ST
A
TUS
PIP
E
_B_DISPLA
Y
_LINE
_
COMP
ARE
_
ST
A
T
US
BLM_IM
A
G
E_BRIGHTNE
S
S
_ST
A
TUS
RE
SE
RVED
OD
D_FIELD_INTE
RRUPT
_ST
A
TUS
EVEN_FIELD_INTE
RRUP
T
_ST
A
TUS
PIPE_B_P
ANEL_SE
LF_REFRE
S
H_ST
A
T
US
ST
AR
T_OF_V
ER
T
ICA
L_BLANK_INTE
RRU
PT
_ST
A
TU
S
P
IPE_B_FRAMEST
AR
T_INTE
RRUP
T
_ST
A
TUS
PIPE
_B_HO
R
IZON
TA
L_BLA
N
K_S
TA
T
US
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW/1C
PIPE_B_UNDERFLOW_STATUS:
This bit is set when an underflow occurs at the
display pipe B. It is cleared by writing a one to this bit. This event will occur naturally
during mode changes, to be effective, it should be cleared after a mode change. This bit
is only valid after Pipe B has been completely configured.
1 = FIFO B Underflow occurred
0 = FIFO B Underflow did not occur
AccessType: One to Clear
30
0b
RW
SPRITE_D_FLIP_DONE_INTERRUPT_ENABLE:
This will enable the consideration of
the Sprite D flip done interrupt status bit in the first line interrupt logic
0 = Sprite D Flip Done Interrupt Disabled
1 = Sprite D Flip Done Interrupt Enabled
29
0b
RW
CRC_ERROR_ENABLE:
This will enable the consideration of the CRC error status bit in
the first line interrupt/status logic.
0 = CRC Error Detect Disabled
1 = CRC Error Detect Enabled
28
0b
RW
CRC_DONE_ENABLE:
This will enable the consideration of the CRC done status bit in
the first line interrupt/status logic.
0 = CRC Done Detect Disabled
1 = CRC Done Detect Enabled
27
0b
RW
PERFORMANCE_COUNTER2_INTERRUPT_ENABLE:
This bit enables the second
performance counter interrupt.
0 = Second Performance Counter2 Interrupt Status Disabled
1 = Second Performance Counter2 interrupt Status Enabled
26
0b
RW
PLANE_B_FLIP_DONE_INTERRUPT_ENABLE:
This will enable the consideration of
the Plane B flip done interrupt status bit in the first line interrupt logic
0 = Plane B flip done Interrupt/Status Disabled
1 = Plane B flip done Interrupt/Status Enabled
25
0b
RW
VERTICAL_SYNC_INTERRUPT_ENABLE:
0 = Vertical Sync Interrupt/Status Disabled
1 = Vertical Sync Interrupt/Status Enabled