Intel E3815 FH8065301567411 Ficha De Dados

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

983

Sprite C Linear Offset Register

Default: 00000000h

14:11

0b

RW

Reserved.

10

0b

RW

This bit indicates that the Sprite C surface data is in tiled memory. 

The tile pitch is specified in bytes in the DSPCSTRIDE register. Only X tiling is supported 

for display surfaces. 

When this bit is set, it affects the hardware interpretation of the DSPCTILEOFF, 

DSPCLINOFF, and DSPCSURFADDR registers. 

0 = Sprite C surface uses linear memory 

1 = Sprite C surface uses X-tiled memory

9:3

0b

RW

Write as zero

2

0b

RW

This bit will force the Sprite C plane to be on the bottom of the Z 

order. If the plane is marked as trusted, it only applies to the Z order of the trusted 

planes. 

0 = Sprite C Z order is determined by the other control bits 

1 = Sprite C is forced to be on the bottom of the Z order.

1

0b

RW

Reserved.

0

0b

RW

With Sprite C and D z-order, bottom control bits, Sprite C plane 

is placed in a specific z-order among other planes in pipe B. 

Display Pipe B Z-orders 

SC 

zorderSC 

bottomSD 

zorderSD 

bottomResulting Pipe Z-order (from bottom to top)Source Keying 

0000PB SC SD CBPB in Black 

1000PB SD SC CBPB in Black 

0001SD PB SC CBuse src keying on SD 

0011SD PB SC CBuse src keying on SD 

1001SD SC PB CBuse src keying on SC 

1011SD SC PB CBuse src keying on SC 

0100SC PB SD CBuse src keying on SC 

1100SC PB SD CBuse src keying on SC 

0110SC SD PB CBuse src keying on SD 

1110SC SD PB CBuse src keying on SD 

0101Not Allowed  

0111Not Allowed  

1101Not Allowed  

1111Not Allowed  

1010Not Allowed  

1011Not Allowed  

 

0: Sprite C z-order is disabled 

1: Sprite C z-order is enabled

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h