Manual Do Utilizadoríndice analíticoCover1Keep safety first in your circuit designs!3Notes regarding these materials3General Precautions on Handling of Product4Important Notice on the Quality Assurance for this LSI5Configuration of This Manual6Preface8Contents13Figures29Tables43Section 1 Overview511.1 Features511.2 Block Diagram571.3 Pin Assignments581.4 Pin functions59Section 2 CPU752.1 Registers752.1.1 General Registers792.1.2 Control Registers812.1.3 System Registers852.1.4 DSP Registers852.2 Data Formats922.2.1 Register Data Format (Non-DSP Type)922.2.2 DSP-Type Data Formats922.2.3 Memory Data Formats942.3 Features of CPU Core Instructions942.4 Instruction Formats982.4.1 CPU Instruction Addressing Modes982.4.2 DSP Data Addressing1012.4.3 CPU Instruction Formats1082.4.4 DSP Instruction Formats1112.5 Instruction Set1172.5.1 CPU Instruction Set1172.6 DSP Extended-Function Instructions1312.6.1 Introduction1312.6.2 Added CPU System Control Instructions1322.6.3 Single and Double Data Transfer for DSP Data Instructions1342.6.4 DSP Operation Instruction Set138Section 3 DSP Operation1493.1 Data Operations of DSP Unit1493.1.1 ALU Fixed-Point Operations1493.1.2 ALU Integer Operations1543.1.3 ALU Logical Operations1553.1.4 Fixed-Point Multiply Operation1573.1.5 Shift Operations1593.1.6 Most Significant Bit Detection Operation1623.1.7 Rounding Operation1653.1.8 Overflow Protection1673.1.9 Data Transfer Operation1683.1.10 Local Data Move Instruction1723.1.11 Operand Conflict1733.2 DSP Addressing1743.2.1 DSP Repeat Control1743.2.2 DSP Data Addressing182Section 4 Clock Pulse Generator (CPG)1934.1 Features1934.2 Input/Output Pins1964.3 Clock Operating Modes1964.4 Register Descriptions1994.4.1 Frequency Control Register (FRQCR)1994.5 Changing the Frequency2014.5.1 Changing the Multiplication Rate2014.5.2 Changing the Division Ratio2014.6 Notes on Board Design202Section 5 Watchdog Timer (WDT)2055.1 Features2055.2 Register Descriptions2065.2.1 Watchdog Timer Counter (WTCNT)2065.2.2 Watchdog Timer Control/Status Register (WTCSR)2075.2.3 Notes on Register Access2095.3 Use of the WDT2095.3.1 Canceling Standbys2095.3.2 Changing the Frequency2105.3.3 Using Watchdog Timer Mode2105.3.4 Using Interval Timer Mode2115.4 Precautions to Take when Using the WDT211Section 6 Power-Down Modes2136.1 Features2136.1.1 Power-Down Modes2136.1.2 Reset2146.1.3 Input/Output Pins2156.2 Register Descriptions2166.2.1 Standby Control Register (STBCR)2166.2.2 Standby Control Register 2 (STBCR2)2176.2.3 Standby Control Register 3 (STBCR3)2186.2.4 Standby Control Register 4 (STBCR4)2206.3 Operation2216.3.1 Sleep Mode2216.3.2 Standby Mode2226.3.3 Module Standby Function2246.3.4 STATUS Pin Change Timings224Section 7 Cache2297.1 Features2297.1.1 Cache Structure2307.2 Register Descriptions2327.2.1 Cache Control Register 1 (CCR1)2327.2.2 Cache Control Register 2 (CCR2)2337.3 Cache Operation2367.3.1 Searching Cache2367.3.2 Read Access2387.3.3 Prefetch Operation2387.3.4 Write Access2387.3.5 Write-Back Buffer2397.3.6 Coherency of Cache and External Memory2397.4 Memory-Mapped Cache2407.4.1 Address Array2407.4.2 Data Array2407.4.3 Usage Examples242Section 8 X/Y Memory2438.1 Features2438.2 X/Y Memory Access from CPU2448.3 X/Y Memory Access from DSP2448.4 X/Y Memory Access from DMAC2458.5 Usage Note2458.6 Sleep Mode2458.7 Address Error245Section 9 Exception Handling2479.1 Register Descriptions2489.1.1 TRAPA Exception Register (TRA)2489.1.2 Exception Event Register (EXPEVT)2499.1.3 Interrupt Event Register 2 (INTEVT2)2499.2 Exception Handling Function2509.2.1 Exception Handling Flow2509.2.2 Exception Vector Addresses2519.2.3 Exception Codes2519.2.4 Exception Request and BL Bit (Multiple Exception Prevention)2519.2.5 Exception Source Acceptance Timing and Priority2529.3 Individual Exception Operations2559.3.1 Resets2559.3.2 General Exceptions2569.4 Exception Processing While DSP Extension Function is Valid2609.4.1 Illegal Instruction Exception and Slot Illegal Instruction Exception2609.4.2 Exception in Repeat Control Period2609.5 Note on Initializing this LSI2669.6 Usage Notes268Section 10 Interrupt Controller (INTC)26910.1 Features26910.2 Input/Output Pins27110.3 Register Descriptions27110.3.1 Interrupt Priority Registers B to J (IPRB to IPRJ)27310.3.2 Interrupt Control Register 0 (ICR0)27510.3.3 Interrupt Control Register 1 (ICR1)27610.3.4 Interrupt Control Register 3 (ICR3)27710.3.5 Interrupt Request Register 0 (IRR0)27810.3.6 Interrupt Mask Registers 0 to 10 (IMR0 to IMR10)27910.3.7 Interrupt Mask Clear Registers 0 to 10 (IMCR0 to IMCR10)28110.4 Interrupt Sources28310.4.1 NMI Interrupt28310.4.2 H-UDI Interrupt28310.4.3 IRQ Interrupts28310.4.4 On-Chip Peripheral Module Interrupts28410.4.5 Interrupt Exception Handling and Priority28510.5 INTC Operation28810.5.1 Interrupt Sequence28810.5.2 Multiple Interrupts29010.6 Notes on Use29010.6.1 Notes on USB Bus Power Control29010.6.2 Timing to Clear an Interrupt Source290Section 11 User Break Controller (UBC)29111.1 Features29111.2 Register Descriptions29311.2.1 Break Address Register A (BARA)29311.2.2 Break Address Mask Register A (BAMRA)29411.2.3 Break Bus Cycle Register A (BBRA)29411.2.4 Break Address Register B (BARB)29611.2.5 Break Address Mask Register B (BAMRB)29711.2.6 Break Data Register B (BDRB)29711.2.7 Break Data Mask Register B (BDMRB)29811.2.8 Break Bus Cycle Register B (BBRB)29911.2.9 Break Control Register (BRCR)30111.2.10 Execution Times Break Register (BETR)30411.2.11 Branch Source Register (BRSR)30411.2.12 Branch Destination Register (BRDR)30511.3 Operation30611.3.1 Flow of the User Break Operation30611.3.2 Break on Instruction Fetch Cycle30711.3.3 Break on Data Access Cycle30811.3.4 Break on X/Y-Memory Bus Cycle30911.3.5 Sequential Break31011.3.6 Value of Saved Program Counter31011.3.7 PC Trace31111.3.8 Usage Examples31211.4 Usage Notes316Section 12 Bus State Controller (BSC)31912.1 Features31912.2 Input/Output Pins32212.3 Area Overview32312.3.1 Area Division32312.3.2 Shadow Area32412.3.3 Address Map32512.3.4 Area 0 Memory Type and Memory Bus Width32712.4 Register Descriptions32712.4.1 Common Control Register (CMNCR)32812.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)33112.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)33612.4.4 SDRAM Control Register (SDCR)36412.4.5 Refresh Timer Control/Status Register (RTCSR)36712.4.6 Refresh Timer Counter (RTCNT)36912.4.7 Refresh Time Constant Register (RTCOR)36912.4.8 Reset Wait Counter (RWTCNT)37012.5 Operating Description37112.5.1 Endian/Access Size and Data Alignment37112.5.2 Normal Space Interface37412.5.3 Access Wait Control37912.5.4 CSn Assert Period Expansion38112.5.5 MPX-I/O Interface38212.5.6 SDRAM Interface38512.5.7 Burst ROM (Clock Asynchronous) Interface42612.5.8 Byte-Selection SRAM Interface42712.5.9 Burst MPX-I/O Interface43212.5.10 Burst ROM Interface (Clock Synchronous)43612.5.11 Wait between Access Cycles43712.5.12 Bus Arbitration44912.5.13 Others451Section 13 Direct Memory Access Controller (DMAC)45513.1 Features45513.2 Input/Output Pins45713.3 Register Descriptions45813.3.1 DMA Source Address Registers (SAR)45913.3.2 DMA Destination Address Registers (DAR)45913.3.3 DMA Transfer Count Registers (DMATCR)45913.3.4 DMA Channel Control Registers (CHCR)46013.3.5 DMA Operation Register (DMAOR)46613.3.6 DMA Extension Resource Selector 0 and 1 (DMARS0, DMARS1)47113.4 Operation47413.4.1 DMA Transfer Flow47413.4.2 DMA Transfer Requests47613.4.3 Channel Priority47913.4.4 DMA Transfer Types48213.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing49013.4.6 Completion of DMA Transfer49413.4.7 Notes on Usage49513.4.8 Notes On DREQ Sampling When DACK is Divided in External Access496Section 14 U Memory50114.1 Features50114.2 U Memory Access from CPU50214.3 U Memory Access from DSP50214.4 U Memory Access from DMAC50214.5 Usage Note50314.6 Sleep Mode50314.7 Address Error503Section 15 User Debugging Interface (H-UDI)50515.1 Features50515.2 Input/Output Pins50615.3 Register Descriptions50715.3.1 Bypass Register (SDBPR)50715.3.2 Instruction Register (SDIR)50715.3.3 Boundary Scan Register (SDBSR)50815.3.4 ID Register (SDID)51715.4 Operation51815.4.1 TAP Controller51815.4.2 Reset Configuration51915.4.3 TDO Output Timing51915.4.4 H-UDI Reset52015.4.5 H-UDI Interrupt52015.5 Boundary Scan52115.5.1 Supported Instructions52115.5.2 Points for Attention52215.6 Usage Notes522Section 16 I2C Bus Interface 2 (IIC2)52316.1 Features52316.2 Input/Output Pins52516.3 Register Descriptions52616.3.1 I2C Bus Control Register 1 (ICCR1)52616.3.2 I2C Bus Control Register 2 (ICCR2)52916.3.3 I2C Bus Mode Register (ICMR)53016.3.4 I2C Bus Interrupt Enable Register (ICIER)53216.3.5 I2C Bus Status Register (ICSR)53416.3.6 Slave Address Register (SAR)53616.3.7 I2C Bus Transmit Data Register (ICDRT)53716.3.8 I2C Bus Receive Data Register (ICDRR)53716.3.9 I2C Bus Shift Register (ICDRS)53716.3.10 NF2CYC Register (NF2CYC)53716.4 Operation53816.4.1 I2C Bus Format53816.4.2 Master Transmit Operation53916.4.3 Master Receive Operation54116.4.4 Slave Transmit Operation54316.4.5 Slave Receive Operation54616.4.6 Clocked Synchronous Serial Format54716.4.7 Noise Filter55116.4.8 Example of Use55216.5 Interrupt Request55616.6 Bit Synchronous Circuit55716.7 Usage Note558Section 17 Compare Match Timer (CMT)55917.1 Features55917.2 Register Descriptions56017.2.1 Compare Match Timer Start Register (CMSTR)56017.2.2 Compare Match Timer Control/Status Register (CMCSR)56117.2.3 Compare Match Counter (CMCNT )56217.2.4 Compare Match Constant Register (CMCOR)56217.3 Operation56317.3.1 Interval Count Operation56317.3.2 CMCNT Count Timing56317.4 Compare Matches56417.4.1 Timing of Compare Match Flag Setting56417.4.2 DMA Transfer Requests and Interrupt Requests56417.4.3 Timing of Compare Match Flag Clearing565Section 18 Multi-Function Timer Pulse Unit (MTU)56718.1 Features56718.2 Input/Output Pins57118.3 Register Descriptions57218.3.1 Timer Control Register (TCR)57418.3.2 Timer Mode Register (TMDR)57818.3.3 Timer I/O Control Register (TIOR)58018.3.4 Timer Interrupt Enable Register (TIER)59818.3.5 Timer Status Register (TSR)60018.3.6 Timer Counter (TCNT)60318.3.7 Timer General Register (TGR)60318.3.8 Timer Start Register (TSTR)60418.3.9 Timer Synchro Register (TSYR)60418.3.10 Timer Output Master Enable Register (TOER)60618.3.11 Timer Output Control Register (TOCR)60718.3.12 Timer Gate Control Register (TGCR)60918.3.13 Timer Subcounter (TCNTS)61118.3.14 Timer Dead Time Data Register (TDDR)61118.3.15 Timer Period Data Register (TCDR)61118.3.16 Timer Period Buffer Register (TCBR)61118.3.17 Bus Master Interface61218.4 Operation61218.4.1 Basic Functions61218.4.2 Synchronous Operation61818.4.3 Buffer Operation62118.4.4 Cascaded Operation62418.4.5 PWM Modes62618.4.6 Phase Counting Mode63118.4.7 Reset-Synchronized PWM Mode63818.4.8 Complementary PWM Mode64118.5 Interrupts66618.5.1 Interrupts and Priority66618.5.2 DMA Activation66818.5.3 A/D Converter Activation66818.6 Operation Timing66918.6.1 Input/Output Timing66918.6.2 Interrupt Signal Timing67418.7 Usage Notes67718.7.1 Module Standby Mode Setting67718.7.2 Input Clock Restrictions67718.7.3 Caution on Period Setting67818.7.4 Conflict between TCNT Write and Clear Operations67818.7.5 Conflict between TCNT Write and Increment Operations67918.7.6 Conflict between TGR Write and Compare Match68018.7.7 Conflict between Buffer Register Write and Compare Match68018.7.8 Conflict between TGR Read and Input Capture68218.7.9 Conflict between TGR Write and Input Capture68318.7.10 Conflict between Buffer Register Write and Input Capture68418.7.11 TCNT2 Write and Overflow/Underflow Conflict in Cascade Connection68418.7.12 Counter Value during Complementary PWM Mode Stop68618.7.13 Buffer Operation Setting in Complementary PWM Mode68618.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag68718.7.15 Overflow Flags in Reset Sync PWM Mode68818.7.16 Conflict between Overflow/Underflow and Counter Clearing68818.7.17 Conflict between TCNT Write and Overflow/Underflow68918.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode69018.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode69018.7.20 Interrupts in Module Standby Mode69018.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection69018.8 MTU Output Pin Initialization69118.8.1 Operating Modes69118.8.2 Reset Start Operation69118.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc.69218.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc.69318.9 Port Output Enable (POE)72318.9.1 Features72318.9.2 Pin Configuration72518.9.3 Register Configuration72518.9.4 Operation731Section 19 Serial Communication Interface with FIFO (SCIF)73519.1 Overview73519.1.1 Features73519.2 Pin Configuration73819.3 Register Description73919.3.1 Receive Shift Register (SCRSR)74019.3.2 Receive FIFO Data Register (SCFRDR)74019.3.3 Transmit Shift Register (SCTSR)74019.3.4 Transmit FIFO Data Register (SCFTDR)74119.3.5 Serial Mode Register (SCSMR)74119.3.6 Serial Control Register (SCSCR)74519.3.7 Serial Status Register (SCFSR)74919.3.8 Bit Rate Register (SCBRR)75719.3.9 FIFO Control Register (SCFCR)76419.3.10 FIFO Data Count Register (SCFDR)76719.3.11 Serial Port Register (SCSPTR)76719.3.12 Line Status Register (SCLSR)77019.4 Operation77119.4.1 Overview77119.4.2 Operation in Asynchronous Mode77319.4.3 Synchronous Operation78319.5 SCIF Interrupts and DMAC79219.6 Usage Notes793Section 20 USB Function Module79720.1 Features79720.1.1 Block Diagram79820.2 Pin Configuration79820.3 Register Descriptions79920.3.1 USB Interrupt Flag Register 0 (USBIFR0)80020.3.2 USB Interrupt Flag Register 1 (USBIFR1)80120.3.3 USB Interrupt Flag Register 2 (USBIFR2)80220.3.4 USB Interrupt Select Register 0 (USBISR0)80320.3.5 USB Interrupt Select Register 1 (USBISR1)80420.3.6 USB Interrupt Enable Register 0 (USBIER0)80420.3.7 USB Interrupt Enable Register 1 (USBIER1)80520.3.8 USB Interrupt Enable Register 2 (USBIER2)80520.3.9 USBEP0i Data Register (USBEPDR0i)80620.3.10 USBEP0o Data Register (USBEPDR0o)80620.3.11 USBEP0s Data Register (USBEPDR0s)80720.3.12 USBEP1 Data Register (USBEPDR1)80720.3.13 USBEP2 Data Register (USBEPDR2)80820.3.14 USBEP3 Data Register (USBEPDR3)80820.3.15 USBEP0o Receive Data Size Register (USBEPSZ0o)80820.3.16 USBEP1 Receive Data Size Register (USBEPSZ1)80920.3.17 USB Trigger Register (USBTRG)80920.3.18 USB Data Status Register (USBDASTS)81020.3.19 USBFIFO Clear Register (USBFCLR)81120.3.20 USBDMA Transfer Setting Register (USBDMAR)81220.3.21 USB Endpoint Stall Register (USBEPSTL)81320.3.22 USB Transceiver Control Register (USBXVERCR)81420.3.23 USB Bus Power Control Register (USBCTRL)81520.4 Operation81620.4.1 Cable Connection81620.4.2 Cable Disconnection81720.4.3 Control Transfer81820.4.4 EP1 Bulk-OUT Transfer (Dual FIFOs)82420.4.5 EP2 Bulk-IN Transfer (Dual FIFOs)82620.4.6 EP3 Interrupt-IN Transfer82820.5 Processing of USB Standard Commands and Class/Vendor Commands82920.5.1 Processing of Commands Transmitted by Control Transfer82920.6 Stall Operations83020.6.1 Forcible Stall by Application83020.6.2 Automatic Stall by USB Function Module83220.7 DMA Transfer83420.7.1 DMA Transfer for Endpoint 183420.7.2 DMA Transfer for Endpoint 283520.8 Example of USB External Circuitry83620.9 USB Bus Power Control Method83920.9.1 USB Bus Power Control Operation83920.9.2 Usage Example of USB Bus Power Control Method84020.10 Notes on Usage84420.10.1 Receiving Setup Data84420.10.2 Clearing FIFO84420.10.3 Overreading or Overwriting Data Register84420.10.4 Assigning Interrupt Source for EP084520.10.5 Clearing FIFO when Setting DMA Transfer84520.10.6 Manual Reset for DMA Transfer84520.10.7 USB Clock84520.10.8 Using TR Interrupt845Section 21 A/D Converter84721.1 Features84721.1.1 Block Diagram84821.1.2 Input Pins84921.1.3 Register Configuration85021.2 Register Descriptions85021.2.1 A/D Data Registers A to D (ADDRA0 to ADDRD0, ADDRA1 to ADDRD1)85021.2.2 A/D Control/Status Registers (ADCSR0, ADCSR1)85121.2.3 A/D0, A/D1 Control Register (ADCR)85421.3 Operation85521.3.1 Single Mode85521.3.2 Multi Mode85621.3.3 Scan Mode85821.3.4 Simultaneous Sampling Operation85921.3.5 A/D Converter Activation by MTU86021.3.6 Input Sampling and A/D Conversion Time86021.4 Interrupt and DMAC Transfer Request86221.5 Definitions of A/D Conversion Accuracy86321.6 Usage Notes86521.6.1 Setting Analog Input Voltage86521.6.2 Processing of Analog Input Pins86521.6.3 Permissible Signal Source Impedance86521.6.4 Influences on Absolute Precision86621.6.5 Stop during A/D Conversion866Section 22 Pin Function Controller (PFC)86922.1 Register Descriptions87322.1.1 Port A Control Register (PACR)87422.1.2 Port B Control Register (PBCR)87622.1.3 Port C Control Register (PCCR)87722.1.4 Port D Control Register (PDCR)87822.1.5 Port E Control Register (PECR)88022.1.6 Port E I/O Register (PEIOR)88222.1.7 Port E MTU R/W Enable Register (PEMTURWER)88322.1.8 Port F Control Register (PFCR)88422.1.9 Port G Control Register (PGCR)88622.1.10 Port H Control Register (PHCR)88822.1.11 Port J Control Register (PJCR)88922.2 I/O Buffer Internal Block Diagram89122.2.1 I/O Buffer with Weak Keeper89122.2.2 I/O Buffer with Open Drain Output89122.3 Notes on Usage892Section 23 I/O Ports89323.1 Port A89323.1.1 Register Description89323.1.2 Port A Data Register (PADR)89423.2 Port B89523.2.1 Register Description89523.2.2 Port B Data Register (PBDR)89623.3 Port C89723.3.1 Register Description89723.3.2 Port C Data Register (PCDR)89823.4 Port D89923.4.1 Register Description90023.4.2 Port D Data Register (PDDR)90023.5 Port E90123.5.1 Register Description90223.5.2 Port E Data Register (PEDR)90223.6 Port F90323.6.1 Register Description90423.6.2 Port F Data Register (PFDR)90423.7 Port G90623.7.1 Register Description90623.7.2 Port G Data Register (PGDR)90723.7.3 Port G Internal Block Diagram90923.8 Port H91023.8.1 Register Description91023.8.2 Port H Data Register (PHDR)91123.9 Port J91223.9.1 Register Description91223.9.2 Port J Data Register (PJDR)913Section 24 List of Registers91524.1 Register Addresses (by functional module, in order of the corresponding section numbers)91624.2 Register Bits92624.3 Register States in Each Operating Mode946Section 25 Electrical Characteristics95725.1 Absolute Maximum Ratings95725.1.1 Power-On Sequence95825.2 DC Characteristics96025.3 AC Characteristics96525.3.1 Clock Timing96625.3.2 Control Signal Timing97025.3.3 AC Bus Timing97325.3.4 Basic Timing97525.3.5 Bus Cycle of Byte-Selection SRAM98225.3.6 Burst ROM Read Cycle98425.3.7 Synchronous DRAM Timing98525.3.8 Peripheral Module Signal Timing100425.3.9 Multi Function Timer Pulse Unit Timing100625.3.10 POE Module Signal Timing100725.3.11 I2C Module Signal Timing100825.3.12 H-UDI Related Pin Timing101025.3.13 USB Module Signal Timing101225.3.14 USB Transceiver Timing101325.3.15 AC Characteristics Measurement Conditions101425.4 A/D Converter Characteristics1015Appendix1017A. Pin States1017A.1 When Other Function is Selected1017A.2 When I/O Port is Selected1021B. Product Lineup1022C. Package Dimensions1023Main Revisions and Additions in this Edition1025Index1027Colophon1033Address List1034Back Cover1036Tamanho: 6 MBPáginas: 1036Language: EnglishAbrir o manual
