Manual Do Utilizadoríndice analíticoCover1Keep safety first in your circuit designs!3Notes regarding these materials3General Precautions on Handling of Product4Configuration of This Manual5Preface6Contents9Figures23Tables31Section 1 Overview351.1 Features351.2 Internal Block Diagram361.3 Pin Description371.3.1 Pin Arrangement371.3.2 Pin Functions in Each Operating Mode381.3.3 Pin Functions43Section 2 CPU472.1 Features472.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU482.1.2 Differences from H8/300 CPU492.1.3 Differences from H8/300H CPU492.2 CPU Operating Modes502.2.1 Normal Mode502.2.2 Advanced Mode522.3 Address Space542.4 Register Configuration552.4.1 General Registers562.4.2 Program Counter (PC)572.4.3 Extended Control Register (EXR)572.4.4 Condition-Code Register (CCR)582.4.5 Initial Register Values592.5 Data Formats602.5.1 General Register Data Formats602.5.2 Memory Data Formats622.6 Instruction Set632.6.1 Table of Instructions Classified by Function642.6.2 Basic Instruction Formats732.7 Addressing Modes and Effective Address Calculation742.7.1 Register Direct—Rn742.7.2 Register Indirect—@ERn742.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)752.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn752.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32752.7.6 Immediate—#xx:8, #xx:16, or #xx:32762.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)762.7.8 Memory Indirect—@@aa:8772.7.9 Effective Address Calculation782.8 Processing States802.9 Usage Notes822.9.1 Note on TAS Instruction Usage822.9.2 Note on STM/LDM Instruction Usage822.9.3 Note on Bit Manipulation Instructions822.9.4 EEPMOV Instruction83Section 3 MCU Operating Modes853.1 MCU Operating Mode Selection853.2 Register Descriptions863.2.1 Mode Control Register (MDCR)863.2.2 System Control Register (SYSCR)873.2.3 Serial Timer Control Register (STCR)893.3 Operating Mode Descriptions903.3.1 Mode 2903.3.2 Mode 3903.4 Address Map91Section 4 Exception Handling934.1 Exception Handling Types and Priority934.2 Exception Sources and Exception Vector Table944.3 Reset954.3.1 Reset Exception Handling954.3.2 Interrupts after Reset964.3.3 On-Chip Peripheral Modules after Reset is Cancelled964.4 Interrupt Exception Handling974.5 Trap Instruction Exception Handling974.6 Stack Status after Exception Handling984.7 Usage Note99Section 5 Interrupt Controller1015.1 Features1015.2 Input/Output Pins1025.3 Register Descriptions1035.3.1 Interrupt Control Registers A to C (ICRA to ICRC)1035.3.2 Address Break Control Register (ABRKCR)1045.3.3 Break Address Registers A to C (BARA to BARC)1055.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)1065.3.5 IRQ Enable Register (IER)1075.3.6 IRQ Status Register (ISR)1075.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Register (WUEMRB)1075.4 Interrupt Sources1105.4.1 External Interrupts1105.4.2 Internal Interrupts1115.5 Interrupt Exception Handling Vector Table1125.6 Interrupt Control Modes and Interrupt Operation1145.6.1 Interrupt Control Mode 01145.6.2 Interrupt Control Mode 11165.6.3 Interrupt Exception Handling Sequence1195.6.4 Interrupt Response Times1205.7 Address Break1215.7.1 Features1215.7.2 Block Diagram1215.7.3 Operation1225.7.4 Usage Notes1225.8 Usage Notes1245.8.1 Conflict between Interrupt Generation and Disabling1245.8.2 Instructions that Disable Interrupts1255.8.3 Interrupts during Execution of EEPMOV Instruction1255.8.4 IRQ Status Register (ISR)125Section 6 Bus Controller (BSC)1276.1 Register Descriptions1276.1.1 Bus Control Register (BCR)1276.1.2 Wait State Control Register (WSCR)128Section 7 I/O Ports1297.1 Port 11347.1.1 Port 1 Data Direction Register (P1DDR)1347.1.2 Port 1 Data Register (P1DR)1347.1.3 Port 1 Pull-Up MOS Control Register (P1PCR)1357.1.4 Pin Functions1357.1.5 Port 1 Input Pull-Up MOS1367.2 Port 21367.2.1 Port 2 Data Direction Register (P2DDR)1367.2.2 Port 2 Data Register (P2DR))1377.2.3 Port 2 Pull-Up MOS Control Register (P2PCR)1377.2.4 Pin Functions1377.2.5 Port 2 Input Pull-Up MOS1387.3 Port 31387.3.1 Port 3 Data Direction Register (P3DDR)1387.3.2 Port 3 Data Register (P3DR)1397.3.3 Port 3 Pull-Up MOS Control Register (P3PCR)1397.3.4 Pin Functions1407.3.5 Port 3 Input Pull-Up MOS1407.4 Port 41417.4.1 Port 4 Data Direction Register (P4DDR)1417.4.2 Port 4 Data Register (P4DR)1417.4.3 Pin Functions1427.5 Port 51447.5.1 Port 5 Data Direction Register (P5DDR)1447.5.2 Port 5 Data Register (P5DR)1447.5.3 Pin Functions1457.6 Port 61467.6.1 Port 6 Data Direction Register (P6DDR)1467.6.2 Port 6 Data Register (P6DR)1477.6.3 Port 6 Pull-Up MOS Control Register (KMPCR)1477.6.4 System Control Register 2 (SYSCR2)1487.6.5 Pin Functions1487.6.6 Port 6 Input Pull-Up MOS1507.7 Port 71517.7.1 Port 7 Input Data Register (P7PIN)1517.7.2 Pin Functions1517.8 Port 81527.8.1 Port 8 Data Direction Register (P8DDR)1527.8.2 Port 8 Data Register (P8DR)1527.8.3 Pin Functions1537.9 Port 91567.9.1 Port 9 Data Direction Register (P9DDR)1567.9.2 Port 9 Data Register (P9DR)1567.9.3 Pin Functions1577.10 Port A1597.10.1 Port A Data Direction Register (PADDR)1597.10.2 Port A Output Data Register (PAODR)1597.10.3 Port A Input Data Register (PAPIN)1607.10.4 Pin Functions1607.10.5 Port A Input Pull-Up MOS1627.11 Port B1637.11.1 Port B Data Direction Register (PBDDR)1637.11.2 Port B Output Data Register (PBODR)1637.11.3 Port B Input Data Register (PBPIN)1647.11.4 Pin Functions1647.11.5 Port B Input Pull-Up MOS1657.12 Ports C, D1667.12.1 Port C and Port D Data Direction Registers (PCDDR, PDDDR)1667.12.2 Port C and Port D Output Data Registers (PCODR, PDODR)1677.12.3 Port C and Port D Input Data Registers (PCPIN, PDPIN)1677.12.4 Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR)1687.12.5 Pin Functions1697.12.6 Input Pull-Up MOS in Ports C and D1697.13 Ports E, F1707.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR)1707.13.2 Port E and Port F Output Data Registers (PEODR, PFODR)1717.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN)1727.13.4 Pin Functions1727.13.5 Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR)1747.13.6 Pin Functions1757.13.7 Input Pull-Up MOS in Ports E and F1757.14 Port G1767.14.1 Port G Data Direction Register (PGDDR)1767.14.2 Port G Output Data Register (PGODR)1777.14.3 Port G Input Data Register (PGPIN)1777.14.4 Pin Functions1787.14.5 Port G Nch-OD Control Register (PGNOCR)1797.14.6 Pin Functions179Section 8 8-Bit PWM Timer (PWM)1818.1 Features1818.2 Input/Output Pins1828.3 Register Descriptions1828.3.1 PWM Register Select (PWSL)1838.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWD0)1858.3.3 PWM Data Polarity Register A (PWDPRA)1858.3.4 PWM Output Enable Register A (PWOERA)1868.3.5 Peripheral Clock Select Register (PCSR)1868.4 Operation1878.4.1 PWM Setting Example1898.4.2 Diagram of PWM Used as D/A Converter1898.5 Usage Notes1908.5.1 Module Stop Mode Setting190Section 9 16-Bit Free-Running Timer (FRT)1919.1 Features1919.2 Input/Output Pins1939.3 Register Descriptions1939.3.1 Free-Running Counter (FRC)1949.3.2 Output Compare Registers A and B (OCRA, OCRB)1949.3.3 Input Capture Registers A to D (ICRA to ICRD)1949.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF)1959.3.5 Output Compare Register DM (OCRDM)1959.3.6 Timer Interrupt Enable Register (TIER)1969.3.7 Timer Control/Status Register (TCSR)1979.3.8 Timer Control Register (TCR)2009.3.9 Timer Output Compare Control Register (TOCR)2019.4 Operation2039.4.1 Pulse Output2039.5 Operation Timing2049.5.1 FRC Increment Timing2049.5.2 Output Compare Output Timing2059.5.3 FRC Clear Timing2059.5.4 Input Capture Input Timing2069.5.5 Buffered Input Capture Input Timing2079.5.6 Timing of Input Capture Flag (ICF) Setting2089.5.7 Timing of Output Compare Flag (OCF) setting2089.5.8 Timing of FRC Overflow Flag Setting2099.5.9 Automatic Addition Timing2099.5.10 Mask Signal Generation Timing2109.6 Interrupt Sources2119.7 Usage Notes2119.7.1 Conflict between FRC Write and Clear2119.7.2 Conflict between FRC Write and Increment2129.7.3 Conflict between OCR Write and Compare-Match2129.7.4 Switching of Internal Clock and FRC Operation2149.7.5 Module Stop Mode Setting215Section 10 8-Bit Timer (TMR)21710.1 Features21710.2 Input/Output Pins22210.3 Register Descriptions22310.3.1 Timer Counter (TCNT)22510.3.2 Time Constant Register A (TCORA)22510.3.3 Time Constant Register B (TCORB)22510.3.4 Timer Control Register (TCR)22610.3.5 Timer Control/Status Register (TCSR)23010.3.6 Time Constant Register (TCORC)23610.3.7 Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A)23610.3.8 Timer Input Select Register (TISR and TISR_B)23610.3.9 Timer Connection Register I (TCONRI)23710.3.10 Timer Connection Register S (TCONRS)23710.3.11 Timer XY Control Register (TCRXY)23810.3.12 Timer AB Control Register (TCRAB)23910.4 Operation24010.4.1 Pulse Output24010.5 Operation Timing24110.5.1 TCNT Count Timing24110.5.2 Timing of CMFA and CMFB Setting at Compare-Match24110.5.3 Timing of Timer Output at Compare-Match24210.5.4 Timing of Counter Clear at Compare-Match24210.5.5 TCNT External Reset Timing24310.5.6 Timing of Overflow Flag (OVF) Setting24310.6 TMR_0 and TMR_1 Cascaded Connection24410.6.1 16-Bit Count Mode24410.6.2 Compare-Match Count Mode24410.7 TMR_Y and TMR_X Cascaded Connection24510.7.1 16-Bit Count Mode24510.7.2 Compare-Match Count Mode24510.7.3 Input Capture Operation24610.8 TMR_B and TMR_A Cascaded Connection24610.8.1 16-Bit Count Mode24610.8.2 Compare-Match Count Mode24610.8.3 Input Capture Operation24710.9 Interrupt Sources24910.10 Usage Notes25010.10.1 Conflict between TCNT Write and Counter Clear25010.10.2 Conflict between TCNT Write and Count-Up25010.10.3 Conflict between TCOR Write and Compare-Match25110.10.4 Conflict between Compare-Matches A and B25110.10.5 Switching of Internal Clocks and TCNT Operation25210.10.6 Mode Setting with Cascaded Connection25310.10.7 Module Stop Mode Setting253Section 11 Watchdog Timer (WDT)25511.1 Features25511.2 Input/Output Pins25711.3 Register Descriptions25711.3.1 Timer Counter (TCNT)25711.3.2 Timer Control/Status Register (TCSR)25811.4 Operation26111.4.1 Watchdog Timer Mode26111.4.2 Interval Timer Mode26311.4.3 RESO Signal Output Timing26411.5 Interrupt Sources26411.6 Usage Notes26511.6.1 Notes on Register Access26511.6.2 Conflict between Timer Counter (TCNT) Write and Increment26611.6.3 Changing Values of CKS2 to CKS0 Bits26611.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode26611.6.5 System Reset by RESO Signal26711.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes267Section 12 Serial Communication Interface (SCI)26912.1 Features26912.2 Input/Output Pins27012.3 Register Descriptions27112.3.1 Receive Shift Register (RSR)27112.3.2 Receive Data Register (RDR)27112.3.3 Transmit Data Register (TDR)27112.3.4 Transmit Shift Register (TSR)27212.3.5 Serial Mode Register (SMR)27212.3.6 Serial Control Register (SCR)27312.3.7 Serial Status Register (SSR)27512.3.8 Serial Interface Mode Register (SCMR)27712.3.9 Bit Rate Register (BRR)27812.3.10 Serial Pin Select Register (SPSR)28312.4 Operation in Asynchronous Mode28312.4.1 Data Transfer Format28412.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode28512.4.3 Clock28612.4.4 SCI Initialization (Asynchronous Mode)28712.4.5 Data Transmission (Asynchronous Mode)28812.4.6 Serial Data Reception (Asynchronous Mode)29012.5 Multiprocessor Communication Function29312.5.1 Multiprocessor Serial Data Transmission29412.5.2 Multiprocessor Serial Data Reception29512.6 Operation in Clocked Synchronous Mode29812.6.1 Clock29812.6.2 SCI Initialization (Clocked Synchronous Mode)29912.6.3 Serial Data Transmission (Clocked Synchronous Mode)30012.6.4 Serial Data Reception (Clocked Synchronous Mode)30212.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)30312.7 Interrupt Sources30512.8 Usage Notes30612.8.1 Module Stop Mode Setting30612.8.2 Break Detection and Processing30612.8.3 Mark State and Break Detection30612.8.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)30612.8.5 Relation between Writing to TDR and TDRE Flag30612.8.6 SCI Operations during Mode Transitions30712.8.7 Switching from SCK Pins to Port Pins310Section 13 I2C Bus Interface (IIC)31113.1 Features31113.2 Input/Output Pins31413.3 Register Descriptions31513.3.1 I2C Bus Data Register (ICDR)31613.3.2 Slave Address Register (SAR)31713.3.3 Second Slave Address Register (SARX)31813.3.4 I2C Bus Mode Register (ICMR)32013.3.5 I2C Bus Control Register (ICCR)32313.3.6 I2C Bus Status Register (ICSR)33113.3.7 DDC Switch Register (DDCSWR)33513.3.8 I2C Bus Extended Control Register (ICXR)33613.3.9 Port G Control Register (PGCTL)34013.4 Operation34113.4.1 I2C Bus Data Format34113.4.2 Initialization34313.4.3 Master Transmit Operation34313.4.4 Master Receive Operation34813.4.5 Slave Receive Operation35513.4.6 Slave Transmit Operation36213.4.7 IRIC Setting Timing and SCL Control36513.4.8 Noise Canceller36813.4.9 Initialization of Internal State36913.5 Interrupt Sources37013.6 Usage Notes37113.6.1 Module Stop Mode Setting381Section 14 Keyboard Buffer Controller38314.1 Features38314.2 Input/Output Pins38414.3 Register Descriptions38514.3.1 Keyboard Control Register H (KBCRH)38514.3.2 Keyboard Control Register L (KBCRL)38714.3.3 Keyboard Data Buffer Register (KBBR)38814.4 Operation38914.4.1 Receive Operation38914.4.2 Transmit Operation39014.4.3 Receive Abort39314.4.4 KCLKI and KDI Read Timing39514.4.5 KCLKO and KDO Write Timing39514.4.6 KBF Setting Timing and KCLK Control39614.4.7 Receive Timing39714.4.8 KCLK Fall Interrupt Operation39814.5 Usage Notes39914.5.1 KBIOE Setting and KCLK Falling Edge Detection39914.5.2 Module Stop Mode Setting400Section 15 Host Interface (LPC)40115.1 Features40115.2 Input/Output Pins40315.3 Register Descriptions40415.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)40515.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)41115.3.3 LPC Channel 3 Address Register (LADR3)41315.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3)41415.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)41515.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)41515.3.7 Status Registers 1 to 3 (STR1 to STR3)41515.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1)42115.3.9 Host Interface Select Register (HISEL)42915.4 Operation43015.4.1 Host Interface Activation43015.4.2 LPC I/O Cycles43115.4.3 A20 Gate43215.4.4 Host Interface Shutdown Function (LPCPD)43515.4.5 Host Interface Serialized Interrupt Operation (SERIRQ)43915.4.6 Host Interface Clock Start Request (CLKRUN)44115.5 Interrupt Sources44215.5.1 IBFI1, IBFI2, IBFI3, and ERRI44215.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ1244215.6 Usage Notes44515.6.1 Module Stop Mode Setting44515.6.2 Notes on Using Host Interface445Section 16 A/D Converter44716.1 Features44716.2 Input/Output Pins44916.3 Register Descriptions45016.3.1 A/D Data Registers A to D (ADDRA to ADDRD)45016.3.2 A/D Control/Status Register (ADCSR)45116.3.3 A/D Control Register (ADCR)45216.4 Operation45316.4.1 Single Mode45316.4.2 Scan Mode45316.4.3 Input Sampling and A/D Conversion Time45516.4.4 External Trigger Input Timing45616.5 Interrupt Sources45716.6 A/D Conversion Accuracy Definitions45716.7 Usage Notes45916.7.1 Permissible Signal Source Impedance45916.7.2 Influences on Absolute Accuracy45916.7.3 Setting Range of Analog Power Supply and Other Pins46016.7.4 Notes on Board Design46016.7.5 Notes on Noise Countermeasures46016.7.6 Module Stop Mode Setting461Section 17 RAM463Section 18 ROM46518.1 Features46518.2 Mode Transitions46718.3 Block Configuration47018.4 Input/Output Pins47118.5 Register Descriptions47118.5.1 Flash Memory Control Register 1 (FLMCR1)47218.5.2 Flash Memory Control Register 2 (FLMCR2)47318.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)47418.6 Operating Modes47518.7 On-Board Programming Modes47518.7.1 Boot Mode47618.7.2 User Program Mode47918.8 Flash Memory Programming/Erasing48018.8.1 Program/Program-Verify48018.8.2 Erase/Erase-Verify48218.9 Program/Erase Protection48418.9.1 Hardware Protection48418.9.2 Software Protection48418.9.3 Error Protection48418.10 Interrupts during Flash Memory Programming/Erasing48518.11 Programmer Mode48618.12 Usage Notes487Section 19 Clock Pulse Generator48919.1 Oscillator49019.1.1 Connecting Crystal Resonator49019.1.2 External Clock Input Method49119.2 Duty Correction Circuit49319.3 Medium-Speed Clock Divider49319.4 Bus Master Clock Select Circuit49319.5 Subclock Input Circuit49419.6 Waveform Forming Circuit49419.7 Clock Select Circuit49519.8 Usage Notes49519.8.1 Note on Resonator49519.8.2 Notes on Board Design495Section 20 Power-Down Modes49720.1 Register Descriptions49720.1.1 Standby Control Register (SBYCR)49820.1.2 Low-Power Control Register (LPWRCR)49920.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)50120.2 Mode Transitions and LSI States50220.3 Medium-Speed Mode50420.4 Sleep Mode50520.5 Software Standby Mode50520.6 Hardware Standby Mode50720.7 Watch Mode50820.8 Subsleep Mode50920.9 Subactive Mode51020.10 Module Stop Mode51120.11 Direct Transitions51120.12 Usage Notes51220.12.1 I/O Port Status51220.12.2 Current Consumption when Waiting for Oscillation Stabilization512Section 21 List of Registers51321.1 Register Addresses (Address Order)51421.2 Register Bits52321.3 Register States in Each Operating Mode53121.4 Register Select Conditions539Section 22 Electrical Characteristics54722.1 Absolute Maximum Ratings54722.2 DC Characteristics54822.3 AC Characteristics55422.3.1 Clock Timing55522.3.2 Control Signal Timing55622.3.3 Timing of On-Chip Peripheral Modules55722.4 A/D Conversion Characteristics56022.5 Flash Memory Characteristics56122.6 Usage Note56322.7 Timing Chart56322.7.1 Clock Timing56322.7.2 Control Signal Timing56522.7.3 On-Chip Peripheral Module Timing566Appendix571A. I/O Port States in Each Processing State571B. Product Codes572C. Package Dimensions573Index575Colphon579Address List580Back Cover582Tamanho: 4 MBPáginas: 582Language: EnglishAbrir o manual