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Справочник Пользователя для Mitsubishi Electronics QD64D2

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OVERVIEW
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CHAPTER1 OVERVIEW
This User's Manual describes the specifications, handling, and programming methods for 
the type QD64D2 4Mpps capable high-speed counter module used together with the 
MELSEC-Q series CPU module.
The QD64D2 has the following input methods.
For details of the input methods, refer to Section 5.1.
Figure 1.1 shows the general operation of the QD64D2.
Figure 1.1 General operation of the QD64D2
•1 multiple of 1 phase pulse 
input   
•2 multiples of 1 phase pulse 
input   
•CW/CCW
•1 multiple of 2 phases pulse 
input
•2 multiples of 2 phases pulse 
input   
•4 multiples of 2 phases pulse 
input
CH2
CH1
QD64D2
1)
2)
4) 
5) 
1)
2)
4) 
5)
1) Pulses to be input to the QD64D2 are counted.
2) Preset value and count value can be latched with external control signal.
3) Status of the I/O signal and buffer memory of the QD64D2 can be checked with the sequence 
program.
 
Also, start/stop of a count, preset, and coincidence output can be performed.
4) When a counter value matches with the set value, an interrupt request can be issued to the 
programmable controller CPU.
5) The present value is compared with comparison point setting value and the coincidence signal can 
be output.
Encoder
Controller
Encoder
Controller
Pulse
Pulse
External
control signal
Preset 
Latch counter
External
control signal
Preset 
Latch counter
Reading/writing 
I/O signal and 
buffer memory
Programmable 
controller CPU
QCPU (Q mode)
Coincidence signal 
output (2 points)
Coincidence signal 
output (2 points)
3)