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Cache and Memory Optimizations
Chapter 5
25112
Rev. 3.06
September 2005
Software Optimization Guide for AMD64 Processors
5.10
Placing Code and Data in the Same 64-Byte Cache
Line
Line
Optimization
❖
Avoid placing code and data together within a cache line, especially if the data becomes
modified.
Application
This optimization applies to:
•
32-bit software
•
64-bit software
Rationale
Sharing code and data in the same 64-byte cache line may cause the L1 caches to thrash
(unnecessarily cast out code or data) in order to maintain coherency between the separate instruction
and data caches. The AMD Athlon 64 and AMD Opteron processors have a cache-line size of 64
bytes.
(unnecessarily cast out code or data) in order to maintain coherency between the separate instruction
and data caches. The AMD Athlon 64 and AMD Opteron processors have a cache-line size of 64
bytes.
For example, consider that a memory-indirect JMP instruction may have the data for the jump table
residing in the same 64-byte cache line as the JMP instruction. This mixing of code and data in the
same cache line results in lower performance.
residing in the same 64-byte cache line as the JMP instruction. This mixing of code and data in the
same cache line results in lower performance.
Do not place critical code at the border between 32-byte-aligned code segments and data segments.
Code at the beginning or end of a data segment should be executed as infrequently as possible or
padded.
Code at the beginning or end of a data segment should be executed as infrequently as possible or
padded.
In summary, avoid self-modifying code and storing data in code segments.