Справочник Пользователя для AMD 250

25112

Rev. 3.06

September 2005

The L2 cache in the AMD Athlon XP, AMD Athlon™ 64, and AMD Opteron processors is 16-way 
associative.

See Appendix B, “Implementation of Write-Combining,” on page 263 for detailed information about 
write-combining.

AMD Athlon 64 and AMD Opteron processors feature an integrated memory controller and 
HyperTransport technology for interfacing to I/O devices. These integrated features, along with other 
logic, bring the Northbridge functionality onto the processor.

AMD Athlon 64 and AMD Opteron processors provide an integrated low-latency, high-bandwidth 
DDR memory controller.

The memory controller supports:

•

DRAM devices that are 4, 8, and 16 bits wide.

•

Interleaving memory within DIMMs.

•

ECC checking with double-bit detection and single-bit correction.

For specifications on a certain processor’s memory controller, see the data sheet for that processor. 
For information on how to program the memory controller, see the BIOS and Kernel Developer’s 
Guide for AMD Athlon

 Processors, order# 26094.

HyperTransport technology is a scalable, high-speed, low-latency, point-to-point, packetized link 
that:

•

Enables data transfer rates of up to 8 Gbytes/s (4 Gbytes/s in each direction simultaneously with a 
16-bit link).

•

Simplifies connectivity by replacing legacy buses and bridges.

•

Reduces latencies and bottlenecks within systems.