Справочник Пользователя для AMD 250
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Implementation of Write-Combining
Appendix B
25112
Rev. 3.06
September 2005
Software Optimization Guide for AMD64 Processors
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WB—Writeback memory type
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One Byte—8 bits
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One Word—16 bits
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Doubleword—32 bits
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Quadword—64 bits or 2 doublewords
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Cache Block—64 bytes or 4 octawords or 8 quadwords
B.2
Programming Details
The following steps are required for programming write-combining on the AMD Athlon 64 and
AMD Opteron processors:
AMD Opteron processors:
1. Verify the presence of an AMD Athlon™ 64 or AMD Opteron processor by using the CPUID
instruction to check for the instruction family code and vendor identification of the processor.
Standard function 0 on AMD processors returns a vendor identification string of
“AuthenticAMD” in registers EBX, EDX, and ECX. Standard function 1 returns the processor
signature in register EAX, where EAX[11:8] contains the instruction family code. For the
AMD Athlon 64 and AMD Opteron processors, the instruction family code is Fh.
Standard function 0 on AMD processors returns a vendor identification string of
“AuthenticAMD” in registers EBX, EDX, and ECX. Standard function 1 returns the processor
signature in register EAX, where EAX[11:8] contains the instruction family code. For the
AMD Athlon 64 and AMD Opteron processors, the instruction family code is Fh.
2. Verify the presence of the MTRRs and the PAT extensions. The presence of the MTRRs is
indicated by bit 12 and the presence of the PAT extensions is indicated by bit 16 of the extended
features bits returned in the EDX register by CPUID function 8000_0001h. See the CPUID
Specification, order# 25481, for more details on the CPUID instruction.
features bits returned in the EDX register by CPUID function 8000_0001h. See the CPUID
Specification, order# 25481, for more details on the CPUID instruction.
3. Enable write-combining. Write-combining is controlled by the MTRRs and PAT extensions.
Write-combining should be enabled for the appropriate memory ranges. For more information on
the MTRRs and the PAT extensions, see volume 2 of the AMD64 Architecture Programmer’s
Manual, order# 24593.
the MTRRs and the PAT extensions, see volume 2 of the AMD64 Architecture Programmer’s
Manual, order# 24593.
B.3
Write-combining Operations
To improve system performance, the AMD Athlon 64 and AMD Opteron processors aggressively
combine multiple memory-write cycles of any data size that address locations within a 64-byte write
buffer that is aligned to a cache-line boundary. The processor continues to combine writes to this
buffer without writing the data to the system, as long as certain rules apply (see Table 12 on page 265
for more information). The data sizes can be bytes, words, doublewords, or quadwords.
combine multiple memory-write cycles of any data size that address locations within a 64-byte write
buffer that is aligned to a cache-line boundary. The processor continues to combine writes to this
buffer without writing the data to the system, as long as certain rules apply (see Table 12 on page 265
for more information). The data sizes can be bytes, words, doublewords, or quadwords.
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WC memory type writes can be combined in any order up to a full 64-byte write buffer.
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WT memory type writes can only be combined up to a fully aligned quadword in the 64-byte
buffer, and must be combined contiguously in ascending order. Combining may be opened at any
buffer, and must be combined contiguously in ascending order. Combining may be opened at any