Справочник Пользователя для Intel D525 AU80610006225AA
Модели
AU80610006225AA
Signal Description
24
Datasheet
2.7
JTAG/ITP Signals
2.8
Error and Thermal Protection
Table 2-12.JTAG/ITP Signals
Signal
Name
Description Direction
Type
TCK
TCK (Test Clock) provides the clock input for the
processor Test Bus (also known as the Test Access Port).
processor Test Bus (also known as the Test Access Port).
I
TAP
OD
TDI
TDI (Test Data In) transfers serial test data into the
processor. TDI provides the serial input needed for JTAG
specification support.
processor. TDI provides the serial input needed for JTAG
specification support.
I
TAP
OD
TDO
TDO (Test Data Out) transfers serial test data out of the
processor. TDO provides the serial output needed for
JTAG specification support.
processor. TDO provides the serial output needed for
JTAG specification support.
O
TAP
OD
TMS
TMS (Test Mode Select) is a JTAG specification support
signal used by debug tools.
signal used by debug tools.
I
TAP
OD
TRST#
TRST# (Test Reset) resets the Test Access Port (TAP)
logic. TRST# must be driven low during power on Reset.
Refer to the Nehalem Processor Debug Port Design Guide
for complete implementation details.
logic. TRST# must be driven low during power on Reset.
Refer to the Nehalem Processor Debug Port Design Guide
for complete implementation details.
I
TAP
OD
Table 2-13.Error and Thermal Protection
Signal
Name
Description Direction
Type
PROCHOT#
PROCHOT# will go active when the processor
temperature monitoring sensor(s) detects that the
processor has reached its maximum safe operation
temperature
Output: This indicates that the processor (core0 and
core1) Thermal Control Circuit has been activated, if
enabled.
Input: This signal can also be driven to the processor to
activate the Thermal Control Circuit in core0 and core1.
This signal does not have on-die termination and must
be terminated on the system board, and 60 Ohm
resistor to Vcc.
temperature monitoring sensor(s) detects that the
processor has reached its maximum safe operation
temperature
Output: This indicates that the processor (core0 and
core1) Thermal Control Circuit has been activated, if
enabled.
Input: This signal can also be driven to the processor to
activate the Thermal Control Circuit in core0 and core1.
This signal does not have on-die termination and must
be terminated on the system board, and 60 Ohm
resistor to Vcc.
I/O
I: CMOS
O: OD
THERMTRIP#
Thermal Trip: The processor protects itself from
catastrophic overheating by use of an internal thermal
sensor. This sensor is set well above the normal
operating temperature to ensure that there are no false
trips. The processor will stop all execution when the
junction temperature exceeds approximately 125 C.
This is signaled to the system by the THERMTRIP# pin.
Refer to the appropriate platform design guide for
termination requirements.
catastrophic overheating by use of an internal thermal
sensor. This sensor is set well above the normal
operating temperature to ensure that there are no false
trips. The processor will stop all execution when the
junction temperature exceeds approximately 125 C.
This is signaled to the system by the THERMTRIP# pin.
Refer to the appropriate platform design guide for
termination requirements.
O
Open
Drain
Drain