Справочник Пользователя для AeroComm Corporation 4424200
3/23/2006
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5.1.5 9600 Baud/Packet Frame (pin 12)
9600_BAUD – When pulled logic Low before applying power or resetting, the transceiver’s serial
interface is forced to a 9600, 8-N-1 (8 data bits, No parity, 1 stop bit) rate. To exit, transceiver must be
reset or power-cycled with 9600_Baud logic High.
9600_BAUD should only be used to recover the radio from an unknown baud rate and should not be
used during normal operation. When 9600_BAUD is pulled logic Low, Broadcast Mode is disabled.
interface is forced to a 9600, 8-N-1 (8 data bits, No parity, 1 stop bit) rate. To exit, transceiver must be
reset or power-cycled with 9600_Baud logic High.
9600_BAUD should only be used to recover the radio from an unknown baud rate and should not be
used during normal operation. When 9600_BAUD is pulled logic Low, Broadcast Mode is disabled.
Packet Frame – When enabled in EEPROM, Packet Frame will transition logic Low at the start of a
received RF packet and transition logic High at the completion of the packet.
received RF packet and transition logic High at the completion of the packet.
5.1.6 RSSI (pin 13)
Received Signal Strength Indicator is used by the Host as an indication of instantaneous signal
strength at the receiver. The Host must calibrate RSSI without a RF signal being presented to the
receiver. Calibration is accomplished by following the steps listed below to find a minimum and
maximum voltage value.
strength at the receiver. The Host must calibrate RSSI without a RF signal being presented to the
receiver. Calibration is accomplished by following the steps listed below to find a minimum and
maximum voltage value.
1) Power up only one Client (no Server) transceiver in the coverage area.
2) Measure the RSSI signal to obtain the minimum value with no other signal present.
3) Power up a Server. Make sure the two transceivers are in close proximity and measure
the Client’s peak RSSI once the Client reports In Range to obtain a maximum value at full
signal strength.
signal strength.
5.1.7 Wr_ENA(EEPROM Write Enable) (pin 14)
Wr_ENA is a direct connection to the Write Enable line on the EEPROM. When logic Low, the
EEPROM’s contents may be changed. When logic High, the EEPROM is protected from accidental
and intentional modification. It is recommended that this line only be Low when an EEPROM write is
desired to prevent unintentional corruption of the EEPROM.
EEPROM’s contents may be changed. When logic High, the EEPROM is protected from accidental
and intentional modification. It is recommended that this line only be Low when an EEPROM write is
desired to prevent unintentional corruption of the EEPROM.
5.1.8 UP_RESET (pin 15)
UP_RESET provides a direct connection to the reset pin on the LT4424 microprocessor. To guarantee
a valid power-up reset, this pin should never be tied Low on power-up. For a valid power-on reset,
reset must be High for a minimum of 50 μs.
a valid power-up reset, this pin should never be tied Low on power-up. For a valid power-on reset,
reset must be High for a minimum of 50 μs.
5.1.9 Command/Data (pin 17)
When logic High, transceiver interprets Host data as transmit data to be sent to other transceivers and
their Hosts. When logic Low, transceiver interprets Host data as command data (see Section 4,
Configuring the LT4424).
their Hosts. When logic Low, transceiver interprets Host data as command data (see Section 4,
Configuring the LT4424).