Техническая Спецификация для Infineon Technologies IC MCU 25 SAK-C167SR-LM HA+ MQFP-144 INF SAK-C167SR-LM HA+
Модели
SAK-C167SR-LM HA+
C167CR
C167SR
Electrical Parameters
Data Sheet
72
V3.3, 2005-02
4.4.4
External Bus Timing
Figure 15
CLKOUT Signal Timing
Variable Memory Cycles
The bus timing shown below is programmable via the BUSCONx registers. The duration
of ALE and two types of waitstates can be selected. This table summarizes the possible
bus cycle durations.
The bus timing shown below is programmable via the BUSCONx registers. The duration
of ALE and two types of waitstates can be selected. This table summarizes the possible
bus cycle durations.
Table 17
CLKOUT Reference Signal
Parameter
Symbol
Limits
Unit
Min.
Max.
CLKOUT cycle time
tc
5
CC
30
1)
1) The CLKOUT cycle time is influenced by the PLL jitter.
For a single CLKOUT cycle (2 TCL) the deviation caused by the PLL jitter is below 1 ns (for
f
CPU
> 25 MHz).
For longer periods the relative deviation decreases (see PLL deviation formula).
ns
CLKOUT high time
tc
6
CC
8
–
ns
CLKOUT low time
tc
7
CC
6
–
ns
CLKOUT rise time
tc
8
CC
–
4
ns
CLKOUT fall time
tc
9
CC
–
4
ns
Table 18
Variable Memory Cycles
Bus Cycle Type
Bus Cycle Duration
Unit
25/33 MHz, 0 Waitstates
Demultiplexed bus cycle
with normal ALE
with normal ALE
4 + 2
× (15 - <MCTC>)
+ 2
× (1 - <MTTC>)
TCL
80 ns/60.6 ns
Demultiplexed bus cycle
with extended ALE
with extended ALE
6 + 2
× (15 - <MCTC>)
+ 2
× (1 - <MTTC>)
TCL
120 ns/90.9 ns
Multiplexed bus cycle with
normal ALE
normal ALE
6 + 2
× (15 - <MCTC>)
+ 2
× (1 - <MTTC>)
TCL
120 ns/90.9 ns
Multiplexed bus cycle with
extended ALE
extended ALE
8 + 2
× (15 - <MCTC>)
+ 2
× (1 - <MTTC>)
TCL
160 ns/121.2 ns
MCT04415
CLKOUT
tc
5
tc
6
7
tc
8
tc
9
tc