Техническая Спецификация для Intel D2500 DF8064101055400

Datasheet - Volume 1 of 2

17

This chapter describes the processor signals. They are arranged in functional groups 

according to their associated interface or category. The following notations are used to 

describe the signal type:

The signal description also includes the type of buffer used for the particular signal.

I

Input Pin

O

Output Pin

I/O

Bi-directional Input/Output Pin

CMOS

CMOS buffers. 1.05 V tolerant

DMI

Direct Media Interface signals. These signals are compatible with PCI Express 

1.0 Signalling Environment AC Specifications but are DC coupled. The buffers 

is 1.05 V/1.08 V and not 3.3 V tolerant.

HVCMOS

High Voltage buffers. 3.3 V tolerant

DDR3

DDR3 buffers: 1.5 V tolerant. When implementing DDR3L, the buffer is 1.35 V 

tolerant.

GTL+

Open Drain Gunning Transceiver Logic signaling technology. Refer to GTL+ I/O 

Specification fro complete details. 

TAP

Test Access Port signal

Analog

Analog reference or output. May be used as a threshold voltage or for buffer 

compensation

Ref

Voltage reference signal

Asynch

This signal is asynchronous and has no timing relationship with any reference 

clock.

LVDS

Low Voltage Differential Signalling. A high speed, low power data transmission 

standard used for display connections to LCD panels.