Техническая Спецификация для Intel D2500 DF8064101055400

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Datasheet - Volume 1 of 2
3
Functional Description
3.1
System Memory Controller
The system memory controller supports DDR3 protocols with one 64 bit wide single 
channel accessing two DIMMs. The controller supports a maximum of two non-ECC 
DDR3 SODIMMs or two un-buffered DDR3 DIMMs, single or double sided; thus allowing 
up to four device ranks. Refreshed SKU of Next Generation Intel Atom Processor based 
Mobile Platform Processors support DDR3/DDR3L.
3.1.1
System Memory Organization Modes
The system memory controller supports only one memory organization mode: single 
channel. In this mode, all memory cycles are directed to a single channel.
3.1.2
System Memory Technology Supported
The system memory controller supports the following DDR3/DDR3L Data Transfer 
Rates, DIMM Modules and DRAM Device Technologies:
DDR3/DDR3L Data Transfer Rates: 800MT/s (6.4 GB/s) and 1066MT/s (8.5 GB/s)
DDR3/DDR3L Memory Down Technology:
— Raw Card B Type supported only.
DDR3 SODIMM Modules (unbuffered, non-ECC)
— Raw Card A = 2 rank of x16 SDRAM (double sided)
— Raw Card B = 1 rank of x8 SDRAM (double sided)
— Raw Card C = 1 rank of x16 SDRAM (single sided)
— Raw Card F = 2 ranks of x8 SDRAM (double Sided)
Note:
x8 means that each SDRAM component has 16/8 data lines. x16 means that each 
SDRAM component has 16 data lines.
DDR3/DDR3L DRAM Device Technology:
Standard 1-Gb and 2-Gb technologies and addressing are supported for both x8 and 
x16 devices. There is no support for SO-DIMMs with different technologies or capacities 
on opposite sides of the same SO-DIMM. If one side of a SO-DIMM is populated, the 
other side is either identical or empty.
Supported DDR3/DDR3L SO-DIMM module configurations
“Single sided” above is a logical term referring to the number of Chip Selects attached 
to the DIMM. A real DIMM may put the components on both sides of the substrate, but 
be logically indistinguishable from single sided DIMM if all components on the DIMM are 
attached to the same Chip Select signal.