Техническая Спецификация для Intel C2338 FH8065501516761
Модели
FH8065501516761
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Controller Characteristics and Operation
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
290
Order Number: 330061-002US
15.4
Controller Characteristics and Operation
15.4.1
Electrical
SMBus physical segments must comply with the high-power DC electrical specifications
as defined in the System Management Bus (SMBus) Specification, Version 2.0.
The maximum capacitance of each SMBus signal pin is 40 pF, which includes the sum of
all device capacitance loads and capacitance of trace length. The absolute value of the
total leakage current for an SMBus physical segment, source, and/or sink, must be less
than 200 µA measured at 0.1 x Vcc and 0.9 x Vcc.
15.4.2
SMBus Behavior on PCIe Reset
When power is applied to an SMBus device, it performs default initialization of internal
state as specified in the System Management Bus (SMBus) Specification, Version 2.0
SMBus device interface logic is not affected by PERST#. This normally allows the
SMBus to support communications when the PCIe* interface cannot.
15.4.3
Addressing and Configuration
An Address Resolution Protocol (ARP) is defined in the System Management Bus
(SMBus) Specification, Version 2.0 as assigning slave addresses to SMBus devices. It is
required that systems that connect the SMBus to PCIe slots implement the ARP for
assignment of SMBus slave addresses to SMBus interface devices on PCIe add-in cards.
The system must execute the ARP on a logical SMBus whenever any PCIe device in an
individual slot associated with the logical SMBus exits the D3
COLD
state. Before
executing the ARP, the system must ensure that all ARP-capable SMBus interface
devices are returned to their default address state.