Техническая Спецификация для Intel E3815 FH8065301567411
Модели
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1985
Default: 00000000h
17.8.30
Port-FIS Base Address Upper 32-bits (PxFBU1)—Offset 18Ch
Access Method
Default: 00000000h
17.8.31
Port-Interrupt Status (PxIS1)—Offset 190h
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FB
RSVD
0
Bit
Range
Default &
Access
Description
31:8
0000000h
RW
FIS Base Address (FB):
Indicates the 32-bit base for received FISes. This address
must be 256-byte aligned as indicated by bits 31:08 being read/write. When FIS-based
switching is in use, this structure is 4KB in length and the address shall be 4KB aligned.
Note that these bits are not reset on a HBA reset.
7:0
0b
RO
RSVD0:
Reserved
Type:
Memory Mapped I/O Register
(Size: 32 bits)
PxFBU1:
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FBU
Bit
Range
Default &
Access
Description
31:0
00000000h
RW
FIS Base Address Upper (FBU):
Indicates the upper 32-bits for the received FIS base
for this port. Note that these bits are not reset on a HBA reset.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ABAR Type:
PCI Configuration Register (Size: 32 bits)
ABAR Reference:
[B:0, D:19, F:0] + 24h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CPD
S
TFE
S
HB
FS
HB
D
S
IFS
INFS
RS
VD0
OF
S
IPMS
PRCS
RS
VD1
DMPS
PCS
DPS
UFS
SD
B
S
DS
S
PS
S
DH
RS