Техническая Спецификация для Intel E3815 FH8065301567411

Intel

®

 Atom™ Processor E3800 Product Family

286

Datasheet

DRAM Timing Register 2

27:26

0h

RO

Reserved

25:24

2h

RW

Row Activation to Row Activation Delay. The minimal time interval between 2 ACT 

commands to any bank in the same DRAM device. Limits peak current profile. 00 - 4 

DRAM Clocks (1KB page DDR3-800, 1066, 1333) (2KB page DDR3-800, LPDDR2-800) 

01 - 5 DRAM Clocks (1KB page DDR3-1600) (2KB page DDR3-1333) 10 - 6 DRAM Clocks 

(2KB page DDR3-1066, 1600. LPDDR3-1333) 11 - 7 DRAM Clocks 

23:20

6h

RW

Row Activation Period. The minimal delay, in DRAM clocks, between ACT 

command and PRE command to same bank. At least equal to tRCD + tCWL + tCCD + 

tWR 0h -14 DRAM Clocks. 0h - Reserved 1h - 15 DRAM Clocks (DDR3-800) 2h - 16 

DRAM Clocks 3h - 17 DRAM Clocks (LPDRR2-800) 4h - 18 DRAM Clocks 5h - 19 DRAM 

Clocks 6h - 20 DRAM Clocks (DDR3-1066) 7h - 21 DRAM Clocks 8h - 22 DRAM Clocks 9h 

- 23 DRAM Clocks (LPDRR2-1066) Ah - 24 DRAM Clocks (DDR3-1333) Bh - 25 DRAM 

Clocks Ch - 26 DRAM Clocks Dh - 27 DRAM Clocks Eh - 28 DRAM Clocks (DDR3-1600. 

LPDRR3-1333) Fh - 29 DRAM Clocks 

19:16

9h

RW

Four Bank Activation Window. A rolling time-frame, in which a maximum of 4 

ACT commands (per rank) can be sent. Limits peak current profile. 0h - Reserved 1h - 

Reserved 2h - 14 DRAM Clocks 3h - 16 DRAM Clocks (1KB page DDR3-800) 4h - 18 

DRAM Clocks 5h - 20 DRAM Clocks (2KB page DDR3-800) (1KB page DDR3-1066, 1333. 

LPDDR2-800) 6h - 22 DRAM Clocks 7h - 24 DRAM Clocks (1KB page DDR3-1600) 8h - 

26 DRAM Clocks 9h - 28 DRAM Clocks (2KB page DDR3-1066. LPDDR2-1066) Ah - 30 

DRAM Clocks (2KB page DDR3-1333) Bh - 32 DRAM Clocks (2KB page DDR3-1600) Ch - 

34 DRAM Clocks (LPDDR3-1333) Others - Reserved 

15:14

0h

RO

Reserved

13:12

0h

RW

CAS to CAS delay. The minimum delay, in DRAM clocks, between 2 RD/WR 

commands. 0h - 4 DRAM Clocks: Functional mode. (DDR3-800, 1066, 1333, 1600) 

(LPDDR2-800, 1066) (LPDDR3-1333) 1h - 12 DRAM Clocks: DFX stretch mode (x2) 2h - 

18 DRAM Clocks: DFX stretch mode (x4) 3h - Reserved

11:8

3h

RW

Write to Prechange. The minimum delay, in DRAM clocks, between a WR 

command and a PRE command to the same bank. Value should be computed as 4 + 

tWCL + tWR. 0h - 14 DRAM Clocks (LPDRR2-800) 1h - 15 DRAM Clocks (DDR3-800) 2h 

- 16 DRAM Clocks 3h - 17 DRAM Clocks (LPDDR2-1066) 4h - 18 DRAM Clocks (DDR3-

1066) 5h - 19 DRAM Clocks 6h - 20 DRAM Clocks 7h - 21 DRAM Clocks (DDR3-1333. 

LPDDR3-1333) 8h - 22 DRAM Clocks 9h - 23 DRAM Clocks Ah - 24 DRAM Clocks (DDR3-

1600) Bh - 25 DRAM Clocks Others - Reserved

7:6

0h

RO

Reserved

5:4

2h

RW

Command Transport Duration. The time period, in DRAM clocks, that a command 

occupies the DRAM command bus. 1N is the DDR3 basic requirement. 2N and 3N are 

extended modes for board signal-integrity. 0h - 1 DRAM Clock (1N) 1h - 2 DRAM Clocks 

(2N) 2h - 3 DRAM Clocks (3N) 

3

0h

RO

Reserved

2:0

0h

RW

CAS Write Latency. The delay, in DRAM clocks, between the internal write 

command and the availability of the first bit of DRAM input data. 0h - 3 DRAM Clocks 

(LPDDR2-800) 1h - 4 DRAM Clocks (LPDDR2-1066) 2h - 5 DRAM Clocks (DDR3-800) 3h 

- 6 DRAM Clocks (DDR3-1066. LPDDR3-1333) 4h - 7 DRAM Clocks (DDR3-1333) 5h - 8 

DRAM Clocks (DDR3-1600) Others - Reserved