Техническая Спецификация для Intel E3815 FH8065301567411
Модели
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2870
Datasheet
register, FIFO Control logic transfers data automatically between register and FIFO as
fast as the system moves it. Data in the FIFO shifts up or down to accommodate the
new word (unless it's an attempted Write to a full Transmit FIFO). Status bits (such as
SSSR.TFL, SSSR.RFL, SSSR.RNE, and SSSR.TNF) show users whether the FIFO is full,
above/below a programmable FIFO trigger threshold, or empty. For Transmit data
transfers (Write from system to SSP peripheral), the register can be loaded (written) by
the system processor anytime it falls below its threshold level when using programmed
I/O. When a data size of less than 32-bits is selected, users should not left-justify data
written to the Transmit FIFO. Transmit logic left-justifies the data and ignores any
unused bits. Received data of less than 32-bits is automatically right-justified in the
Receive FIFO. When the Enhanced SSP is programmed for National Semiconductor
Microwire* frame format and if the size for Transmit data is 8-bits as selected by
SSCR1.MWDS=0, then the most significant 24-bits are ignored. Similarly, if the size for
the Transmit data is 16-bit as selected by SSCR1.MWDS=1, then most significant 16-
bits are ignored. The SSCR0.DSS field controls the Receive data size.
Access Method
Default: 00000000h
21.12.6
SSP Time-Out Regsiter (SSTO)—Offset 28h
The Enhanced SSP Time-Out registers have single bit fields that specify the time-out
value used to signal a period of inactivity within the Receive FIFO. Note that Writes to
reserved bits must be zeroes and reads are undetermined.
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
SSDR:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DA
TA
Bit
Range
Default &
Access
Description
31:0
00000000h
RO
Data (DATA):
Data word to be written to/read from transmit/receive FIFO. When
reading from this register when the SSP is disabled (SSE=0) then this will return
indeterminate data.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
SSTO:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSV
D
TIME
OUT