Техническая Спецификация для Intel E3815 FH8065301567411
Модели
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
294
Datasheet
12.3.10
DSCH (DSCH)—Offset 9h
DRAM Scheduler Control
Access Method
Default: 00071108h
19:18
0h
RO
Rsvd_19_18_DRFC:
Reserved
17:16
1h
RW
REFCNTMAX:
Refresh Max tREFI Interval. The maximum interval between ant two REF
commands per rank. JEDEC allows a maximum of 9 x tREFI intervals. 0h - 6 x tREFI 1h
- 7 x tREFI 2h - 8 x tREFI 3h - 9 x tREFI Should not be changed after initial setting.
15
0h
RO
Rsvd_15_DRFC:
Reserved
14:12
2h
RW
tREFI:
Refresh Period. Specifies the average time between sending REF commands to
DRAM. The Dunit will guarantee that the average time is met, but maintains a certain
degree of flexibility in the exact REF scheduling in order to increase overall performance.
0h - Refresh disabled 1h - Reserved for pre-silicon simulation 2h - 3.9 s (Extended
Temperature Range, 85-95 C) 3h - 7.8 s (Normal Temperature Range, 0-85 C)
11:8
Ch
RW
REFWMPNC:
Refresh Panic Watermark. When the refresh debit counter, per rank, is
greater than this value, the Dunit will send a REF command even if there are some
pending requests and regardless of the PMI status level. See DDR3 spec for Refresh
Postponing/Pulling-In flexibility. May be changed to functional value after init sequence.
Value should be greater than, or equal, to REFWMHI. 0h - Reserved 1h - Reserved 2h -
Reserved 3h - Reserved 4h - Reserved 5h - Reserved 6h - Reserved 7h - Postpone 2 REF
commands 8h - Postpone 3 REF commands 9h - Postpone 4 REF commands Ah -
Postpone 5 REF commands Bh - Postpone 6 REF commands Ch - Postpone 7 REF
commands Dh - Postpone 8 REF commands Others - Reserved
7:4
Ah
RW
REFWMHI:
Refresh High Watermark. When the refresh debit counter, per rank, is
greater than this value, the Dunit will send a REF command even if there are some
pending requests to the rank but not if the PMI status is equal to 3. See DDR3 spec for
Refresh Postponing/Pulling-In flexibility. May be changed to functional value after init
sequence. Value should be greater than, or equal, to REFWMLO. 0h - Reserved 1h -
Reserved 2h - Reserved 3h - Reserved 4h - Reserved 5h - Reserved 6h - Reserved 7h -
Postpone 2 REF commands 8h - Postpone 3 REF commands 9h - Postpone 4 REF
commands Ah - Postpone 5 REF commands Bh - Postpone 6 REF commands Ch -
Postpone 7 REF commands Dh - Postpone 8 REF commands Others - Reserved
3:0
7h
RW
REFWMLO:
Opportunistic Refresh Watermark. When the refresh debit counter, per
rank, is greater than this value, the Dunit will send a REF command only if there are no
pending requests to the rank and the PMI status is less than 3. See DDR3 spec for
Refresh Postponing/Pulling-In flexibility. May be changed to functional value after init
sequence. 0h - Reserved 1h - Reserved 2h - Reserved 3h - Reserved 4h - Reserved 5h -
Reserved 6h - Reserved 7h - Postpone 2 REF commands 8h - Postpone 3 REF commands
9h - Postpone 4 REF commands Ah - Postpone 5 REF commands Bh - Postpone 6 REF
commands Ch - Postpone 7 REF commands Dh - Postpone 8 REF commands Others -
Reserved
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Message Bus Register
(Size: 32 bits)
Offset:
Op Codes:
h - Read, h - Write
h - Read, h - Write