Техническая Спецификация для Intel E3815 FH8065301567411
Модели
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
590
Datasheet
Default: 00000000h
14.10.153 VTOTAL_A—Offset 6000Ch
Pipe A Vertical Total Register
Access Method
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SE
RVED
PIP
E
_A_HORIZ
ON
TA
L_SY
N
C
_END
RESE
RVE
D
_1
PIP
E
_A_HORIZ
ON
TA
L_SY
N
C
_ST
A
R
T
Bit
Range
Default &
Access
Field Name (ID): Description
31:29
0b
RW
RESERVED:
Write as zero.
28:16
0b
RW
PIPE_A_HORIZONTAL_SYNC_END:
This 13-bit field specifies the horizontal Sync
End position expressed in terms of the absolute pixel number relative to the horizontal
active display start. The value programmed should be the HSYNC End pixel position,
where the first active pixel is considered position 0; the second active pixel is considered
position 1, etc.
The number of clocks in the sync period needs to be a multiple of two when driving data
out the LVDS port in two channel mode. This value should be greater than the horizontal
sync start position and would be loaded with the Active+RightBorder+FrontPorch+Sync-
1.
15:13
0b
RW
RESERVED_1:
Read Only.
12:0
0b
RW
PIPE_A_HORIZONTAL_SYNC_START:
This 13-bit field specifies the horizontal Sync
Start position expressed in terms of the absolute pixel number relative to the horizontal
active display start. The value programmed should be the HSYNC Start pixel position,
where the first active pixel is considered position 0; the second active pixel is considered
position 1, etc. Note that when HSYNC Start is programmed equal to HBLANK Start,
both HSYNC and HBLANK will be asserted on the same pixel clock. It should never be
programmed to less than HBLANK start.
The number of cycles from the beginning of the line needs to be a multiple of two when
driving data out the LVDS port in two channel mode. This register should not be less
than the horizontal active end. This register should be loaded with the
Active+RightBorder+FrontPorch-1.