Техническая Спецификация для Intel E3815 FH8065301567411

Intel

®

 Atom™ Processor E3800 Product Family

98

Datasheet

1.

This delay is typically created from an RC circuit.

2.

The oscillator startup times are component and design specific. A crystal oscillator can take several 

second to reach a large enough voltage swing. A silicon oscillator can have startups times <10 ms.

The timings shown in 

 

occur when a board event such as AC power is applied 

or power management controller (PMIC) power button is pressed. The following occurs:

1. Suspend (SUS/Always On) wells ramp in the order shown.

2. The external power management controller de-asserts PMC_RSMRST# after the 

suspend rails become stable.

3. PMC_SUSCLK will begin toggling after the de-assertion of PMC_RSMRST#.

4. The system is now in S4/S5 state. Depending on policy bits 

(GEN_PMCON1.PWR_FLR & GEN_PMCON1.AG3E), the SoC either waits for a wake 
event to transition to S0 or continues to S0 state automatically.

5. The transition from S4/S5 to S0 is initiated.

6. The SoC de-asserts PMC_SLP_S4#, and the DRAM (VDD/Un-switched) well ramps.

7. After the DRAM power rail ramp, the external power management controller drives 

DRAM_VDD_S4_PWROK high.

8. The SoC de-asserts PMC_SLP_S3#, and the Core (S0/Switched On) wells ramp in 

the order shown.

9. After all of Core power rails are stable, external power management controller 

drives PMC_CORE_PWROK and DRAM_CORE_PWROK to HIGH, the SoC will then 

t1

RTC_VCC to ILB_RTC_TEST# 

and 

ILB_RTC_RTC# 

de-assertion

9

-

ms

RTC_VCC

•

ILB_RTC_TES
T# & 

ILB_RTC_RTC

#

ILB_RTC_CLK

Osc Startup

Clock Valid

t1