Справочник Пользователя для Infineon 1024MB, 800MHz, DDR II, PC6400, CL6 HYS64T128000EU-2.5C2
Модели
HYS64T128000EU-2.5C2
HYS[64/72]T512020EU–[25F/2.5/3S]–A
Unbuffered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.0, 2008-06
4
06112008-YHWK-B105
1.2
Description
The Qimonda HYS[64/72]T512020EU–[25F/2.5/3S]–A
module family are Unbuffered DIMM modules “UDIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 512M
module family are Unbuffered DIMM modules “UDIMMs”
with 30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 512M
× 64 (4GB) and as
ECC modules in 512M
× 72 (4GB) in organization and
density, intended for mounting into 240-pin connector
sockets.
sockets.
The memory array is designed with 2 Gbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
2
PROM
device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
the second 128 bytes are available to the customer.
TABLE 2
Ordering Information
TABLE 3
Address Format
1) This
t
PREA
value is the minimum value at which this chip will be functional.
2) Precharge-All command for an 8 bank device will equal to
t
RP
+ 1 ×
t
CK
or
t
nRP
+ 1 × nCK, depending on the speed bin,
where
t
nRP
= RU{
t
RP
/
t
CK(avg)
} and
t
RP
is the value for a single bank precharge.
Product Type
1)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
Compliance Code
2)
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400E–555–12–G0" where 6400E
means Unbuffered DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency =5,
Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.2 and produced
on the Raw Card "G".
Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.2 and produced
on the Raw Card "G".
Description
SDRAM Technology
PC2-6400 (5-5-5)
HYS64T512020EU-25F-A
4GB 2R
×8 PC2–6400U–555–12–E0
2 Ranks, Non-ECC
2Gbit (
×8)
HYS72T512020EU-25F-A
4GB 2R
×8 PC2–6400E–555–12–G0
2 Ranks, ECC
2Gbit (
×8)
PC2-6400 (6-6-6)
HYS64T512020EU-2.5-A
4GB 2R
×8 PC2–6400U–666–12–E0
2 Ranks, Non-ECC
2Gbit (
×8)
HYS72T512020EU-2.5-A
4GB 2R
×8 PC2–6400E–666–12–G0
2 Ranks, ECC
2Gbit (
×8)
PC2-5300 (5-5-5)
HYS64T512020EU-3S-A
4GB 2R
×8 PC2–5300U–555–12–E0
2 Ranks, Non-ECC
2Gbit (
×8)
HYS72T512020EU-3S-A
4GB 2R
×8 PC2–5300E–555–12–G0
2 Ranks, ECC
2Gbit (
×8)
DIMM
Density
Density
Module
Organization
Organization
Memory
Ranks
Ranks
ECC/
Non-ECC
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
Card
4GB
512M
× 64
2
Non-ECC
16
15/3/10
E
4GB
512M
× 72
2
ECC
18
15/3/10
G