Справочник Пользователя для Mitsubishi Electronics Mitsubishi Digital Electronics Video Gaming Accessories FX3G
301
FX
3G
/FX
3U
/FX
3UC
Series Programmable Controllers
Programming Manual - Basic & Applied Instruction Edition
11 Rotation and Shift Operation – FNC 30 to FNC 39
11.6 FNC 35 – SFTL / Bit Shift Left
11
FN
C
C
30
-FN
C
C
39
R
otati
on and
on and
Shi
ft
ft
12
FNC4
0-F
0-F
NC4
9
D
ata O
per
ati
per
ati
on
13
FN
C
C
50-FN
C
59
H
igh S
pe
ed
P
rocessing
14
FM
C
C
60-FN
C
69
H
andy
In
st
ru
ct
ion
15
FNC7
0-F
0-F
NC7
9
Ex
ter
nal FX
I/O
D
evice
16
FN
C
C
80-FN
C
89
Ext
ernal
FX
ernal
FX
De
vic
vic
e
17
FN
C
100-
FN
FN
C
10
9
Da
ta
Transf
er 2
er 2
18
FN
C
110-
FN
FN
C
139
Floati
ng Poi
nt
19
FN
C
14
0-F
N
C
149
Da
ta
O
per
at
at
ion 2
20
FN
C
150-
FN
FN
C
159
Posit
ioning
C
ont
ro
ro
l
11.6
FNC 35 – SFTL / Bit Shift Left
Outline
This instruction shifts bit devices of the specified bit length leftward by the specified number of bits.
After shift, the bit device
After shift, the bit device
is transferred by "n2" bits from the least significant bit.
1. Instruction format
2. Set data
*1.
Do not set a negative value to the number of bits to be shifted leftward.
3. Applicable devices
S: "D
.b" is available only in FX
3U
and FX
3UC
PLCs. However, index modifiers (V and Z) are not available.
Explanation of function and operation
1. 16-bit operation (SFTL and SFTLP)
For "n1" bits (shift register length) starting from
, "n2" bits are shifted leftward ([1] and [2] shown below).
After shift, "n2" bits from
are transferred to "n2" bits from
([3] shown below).
Operand Type
Description
Data Type
Head bit device number to be stored to the shift data after leftward shift
Bit
Head bit device number to be shifted leftward
Bit
n1
Bit length of the shift data n2
≤ n1 ≤ 1024
16-bit binary
n2
Number of bits to be shifted leftward n2
≤ n1 ≤ 1024
*1
16-bit binary
Oper-
and
Type
Bit Devices
Word Devices
Others
System User
Digit Specification
System User
Special
Unit
Index
Con-
stant
stant
Real
Number
Charac-
ter String
Pointer
X Y M T C S D
.b KnX KnY KnM KnS T C D R U
\G
V Z Modify K H
E
"
"
P
3 3 3
3
S
3
3 3
3
3
n1
3 3
n2
3 3
3 3
S
P
FNC 35
SFTL
16-bit Instruction
9 steps
Mnemonic
Operation Condition
Continuous
Operation
Pulse (Single)
Pulse (Single)
Operation
SFTL
SFTLP
−
−
−
Mnemonic
Operation Condition
32-bit Instruction
S
D
S
D
D
S
D
+8
+2
n2 (in the case of "n2=3")
n1 (in the case of "n1=9")
[1]
Overflow (data to
be deleted)
+1
D
+7 +6
+5
D
+4 +3
+8
D
+7 +6
+5 +4 +3 +2
D
+1
to +5 before shift (n2=3)
D
[3] Copy
[2]
"n2" bits are
shifted rightward
(n2=3).
+2 to before shift (n2=3)
S
+2 +1
Before
execution
After
execution
S
S
S
D
D
D
D
D
D
D
S
D
D
D
D
D
D
D
D
Command
input
FNC 35
SFTLP
SFTLP
n1
n2
D
S