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FX
3G
/FX
3U
/FX
3UC
 Series Programmable Controllers
Programming Manual - Basic & Applied Instruction Edition
13 High Speed Processing – FNC 50 to FNC 59
13.5 FNC 54 – HSCR / High Speed Counter Reset
11
FN
C
30
-FN
C
39
R
otati
on and 
Shi
ft
12
FNC4
0-F
NC4
9
D
ata O
per
ati
on
13
FN
C
50-FN
C
59
H
igh S
pe
ed 
P
rocessing
14
FM
C
60-FN
C
69
H
andy 
In
st
ru
ct
ion
15
FNC7
0-F
NC7
9
Ex
ter
nal FX
 I/O
 
D
evice
16
FN
C
80-FN
C
89
Ext
ernal
 FX 
De
vic
e
17
FN
C
100-
FN
C
10
9
Da
ta
 
Transf
er 2
18
FN
C
110-
FN
C
139
Floati
ng Poi
nt
19
FN
C
14
0-F
N
C
149
Da
ta
 
O
per
at
ion 2
20
FN
C
150-
FN
C
159
Posit
ioning 
C
ont
ro
l
13.5
FNC 54 – HSCR / High Speed Counter Reset
Outline
This instruction compares the value counted by a high speed counter with a specified value at each count, and
immediately resets an external output (Y) when both values become equivalent to each other.
1. Instruction format
2. Set data
3. Applicable devices
S1: "D….b" is available only in FX
3U
 and FX
3UC
 PLCs. However, index modifiers (V and Z) are not available.
S2: The same counter as 
 can be specified also.  (Refer to the program example shown later.)
S3: This function is supported only in FX
3U
/FX
3UC
 PLCs.
Explanation of function and operation
1. 32-bit operation (DHSCR)
When the current value of a high speed counter (C235 to C255) specified in 
 becomes the comparison value
[
+1, 
] (for example, when the current value changes from "199" to "200" or from "201" to "200" if the
comparison value is K200), the bit device 
 is reset (set to OFF) regardless of the operation cycle.  In this
instruction, the comparison processing is executed after the counting processing in the high speed counter.
Operation
When the present value of the high speed counter C255 changes (counts) from "99" to "100" or from "101" to "100",
Y010 is reset (output refresh).
Operand Type
Description
Data Type
Data to be compared with the current value of a high speed counter or word device
number storing the data to be compared
32-bit binary
Device number of a high speed counter [C235 to C255]
32-bit binary
Bit device number to be reset (set to OFF) when both values become equivalent each
other.
Bit
Oper-
and 
Type
Bit Devices
Word Devices
Others
System User
Digit Specification
System User
Special 
Unit
Index
Constant
Real 
Number
Charac-
ter String
Pointer
X
Y
M T C S D….b KnX KnY KnM KnS T C D R U…\G… V Z Modify
K
H
E
"…"
P
3
3
3
3
3 3 3 3
S3
3
3
3
3
3
3
3
3
3
S1
S2
3
Mnemonic
Operation Condition
32-bit Instruction
13 steps DHSCR
Continuous
Operation
16-bit Instruction
Mnemonic
Operation Condition
FNC 54
HSCR
D
  
S
1
  
S
2
  D
  
S
1
  
S
2
  D
  
S
2
  
S
2
  
S
1
  
S
1
   
D
=
Reset.
Comparison
value
Comparison
source
Output
destination
S
1
 ‚
S
2
 ‚
D ‚
K2,147,483,647
FNC 54
DHSCR
S
2
 ‚
S
1
 ‚
D ‚
S
2
 ‚
Command
input
K100 = C255 
→ Y010
C255
K2,147,483,647
FNC 54
DHSCR
K100
C255
Y010
Reset.
Comparison
value
Comparison
source
Output
destination
M8000
RUN
monitor