Справочник Пользователя для Mentor fastscan and flextest v8.6_4
Test Pattern File Formats
FlexTest Test Pattern File Format
FastScan and FlexTest Reference Manual, V8.6_4
4-29
SET PAttern Source Internal | {{External filename} [-Ascii | -Table |
-Vcd][-Control control_filename] [-NOPadding]}
Example of the LSI Logic Extended VCD Plus Format Patterns
$date March 2, 1997 10:05:01 $end
$version VERILOG-XL 2.3 $end
$timescale 1 ns $end
$scope module adder $end
$var port 1 <0 carry
$var port 4 <1 data
$var port 1 <2 test
$var port 1 <3 write
$upscope $end
$enddefinitions $end
#0
pD 6 0 <0
pU 0 6 <1
pD 6 0 <2
pDDDD 6666 0000 <3
#10
pL 6 0 <1
#100
pX 6 0 <2
$version VERILOG-XL 2.3 $end
$timescale 1 ns $end
$scope module adder $end
$var port 1 <0 carry
$var port 4 <1 data
$var port 1 <2 test
$var port 1 <3 write
$upscope $end
$enddefinitions $end
#0
pD 6 0 <0
pU 0 6 <1
pD 6 0 <2
pDDDD 6666 0000 <3
#10
pL 6 0 <1
#100
pX 6 0 <2
VCD Reader Control File Commands
Following commands are supported in the control file of the VCD Reader.
1. Add Timeplate timeplate_name period data_sample_time offset
[pulse_width]
o
This command adds a timeplate. Timeplates are used to defined the
waveforms for primary input pins. All time values in this command
must be based upon the timescale that appears in the VCD file (for
example, line 3 of
waveforms for primary input pins. All time values in this command
must be based upon the timescale that appears in the VCD file (for
example, line 3 of
Note
The above usage is for FlexTest only.