Справочник Пользователя для Intel 8XC196MH
8XC196MC, MD, MH USER’S MANUAL
B-14
AINC#
I
Auto Increment
During slave programming, this active-low input enables the auto-increment
feature. (Auto increment allows reading or writing of sequential OTPROM
locations, without requiring address transactions across the PBUS for each
read or write.) AINC# is sampled after each location is programmed or dumped.
If AINC# is asserted, the address is incremented and the next data word is
programmed or dumped.
feature. (Auto increment allows reading or writing of sequential OTPROM
locations, without requiring address transactions across the PBUS for each
read or write.) AINC# is sampled after each location is programmed or dumped.
If AINC# is asserted, the address is incremented and the next data word is
programmed or dumped.
AINC# is multiplexed with P2.4 and COMP0.
ALE
O
Address Latch Enable
This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus. ALE differs from ADV#
in that it does not remain active during the entire bus cycle.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus. ALE differs from ADV#
in that it does not remain active during the entire bus cycle.
An external latch can use this signal to demultiplex the address from the
address/data bus.
address/data bus.
ALE is multiplexed with P5.0 and ADV#.
ANGND
GND
Analog Ground
ANGND must be connected for A/D converter and port 0 operation (also Port 1
on the 8XC196MC and MD). ANGND and V
on the 8XC196MC and MD). ANGND and V
SS
should be nominally at the same
potential.
BCLK1:0
(MH only)
(MH only)
I
Baud Clock 0 and 1
BCLK0 and 1 are alternate clock sources for the baud-rate generator input. The
maximum input frequency is F
maximum input frequency is F
XTAL
1
/4.
BCLK0 is multiplexed with P2.1, SCLK0#, and PALE#. BCLK1 is multiplexed
with P2.7 and SCLK1#.
with P2.7 and SCLK1#.
BHE#
O
Byte High Enable
†
During 16-bit bus cycles, this active-low output signal is asserted for word and
high-byte reads and writes to external memory. BHE# indicates that valid data
is being transferred over the upper half of the system data bus. Use BHE#, in
conjunction with AD0, to determine which memory byte is being transferred
over the system bus:
high-byte reads and writes to external memory. BHE# indicates that valid data
is being transferred over the upper half of the system data bus. Use BHE#, in
conjunction with AD0, to determine which memory byte is being transferred
over the system bus:
BHE#
AD0
Byte(s) Accessed
0
0
both bytes
0
1
high byte only
1
0
low byte only
BHE# is multiplexed with P5.5 and WRH#.
†
The chip configuration register 0 (CCR0) determines whether this pin
functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
WRH#.
functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
WRH#.
Table B-6. Signal Descriptions (Continued)
Name
Type
Description