Инструкции для Fujitsu FR81S

Содержание

• CHAPTER 1: OVERVIEW

  39
  • 1. Overview

    40
  • 2. Features

    41
    • 2.1. FR81S CPU Core

      42
    • 2.2. Peripheral Functions

      43
  • 3. Product Line-up

    46
  • 4. Function overview

    58
  • 5. Block Diagram

    62
  • 6. Memory Map

    68
  • 7. Pin Assignment

    70
  • 8. Device Package

    76
  • 9. Explanation of Pin Functions

    83
    • 9.1. Pins of Each Function

      94
      • 9.1.1. Pins of A/D converter (ch.0 to ch.47)

        95
      • 9.1.2. Pins of CAN (ch.0 to ch.2)

        97
      • 9.1.3. Pins of D/A converter (ch.0 to ch.1)

        98
      • 9.1.4. Pins of External interrupt input

        99
      • 9.1.5. Pins of Multi-function serial interface (ch.0 to ch.11)

        100
      • 9.1.6. Pins of PPG (ch.0 to ch.47)

        102
      • 9.1.7. Pin of RTC

        105
      • 9.1.8. Pins of Up/down counter

        106
      • 9.1.9. Pins of Output compare (ch.0 to ch.5: 16bit, ch.6 to ch.11: 32bit)

        107
      • 9.1.10. Pins of Input capture (ch.0 to ch.3: 16bit, ch.4 to ch.9: 32bit)

        108
      • 9.1.11. Pins of Free-run timer (ch.0 to ch.2: 16bit, ch.3 to ch.5: 32bit)

        109
      • 9.1.12. Pins of Base timer (ch.0, ch.1)

        110
      • 9.1.13. Pins of Reload timer (ch.0 to ch.7)

        111
      • 9.1.14. Pins of External Bus interface

        112
      • 9.1.15. Pins of Waveform generator (ch.0 to ch.5)

        114
      • 9.1.16. Pin of Clock monitor

        115
      • 9.1.17. Pins of Port Function (General-Purpose I/O)

        116
      • 9.1.18. Other Pins

        120
  • 10. I/O Circuit Types

    121
• CHAPTER 2: HANDLING THE DEVICE

  125
  • 1. Handling Precautions

    126
  • 2. Handling Device

    130
  • 3. Application Notes

    133
    • 3.1. Function Switching of a Multiplexed Port

      134
    • 3.2. Low-power Consumption Mode

      135
    • 3.3. Notes When Writing Data in a Register Having the Status Flag

      136
• CHAPTER 3: CPU

  137
  • 1. Overview

    138
  • 2. Features

    139
  • 3. CPU Operating Description

    141
    • 3.1. CPU Operating Status

      142
      • 3.1.1. Reset State

        143
      • 3.1.2. Normal Run State

        144
      • 3.1.3. Low-power Consumption State

        145
      • 3.1.4. Debug Run State

        146
  • 4. Pipeline Operation

    147
  • 5. Floating Point Operation Processing

    148
  • 6. Data Structure

    149
  • 7. Addressing

    150
  • 8. Programming Model

    151
    • 8.1. General-purpose Registers, Dedicated Registers, and Floating Point Registers

      152
    • 8.2. System Register

      153
  • 9. Reset and EIT Processing

    154
    • 9.1. Reset

      155
    • 9.2. EIT Processing

      156
    • 9.3. Vector Table

      157
  • 10. Memory Protection Function (MPU)

    159
    • 10.1. Overview

      160
    • 10.2. List of Registers

      161
    • 10.3. Description of Registers

      162
      • 10.3.1. MPU Control Register : MPUCR

        163
      • 10.3.2. Instruction Access Protection Violation Address Register : IPVAR

        166
      • 10.3.3. Instruction Access Protection Violation Status Register : IPVSR

        167
      • 10.3.4. Data Access Protection Violation Address Register :DPVAR

        169
      • 10.3.5. Data Access Protection Violation Status Register : DPVSR

        170
      • 10.3.6. Data Access Error Address Register : DEAR

        172
      • 10.3.7. Data Access Error Status Register : DESR

        173
      • 10.3.8. Protection Area Base Address Register 0 to 7 : PABR0 to PABR7

        175
      • 10.3.9. Protection Area Control Register 0 to 7 : PACR0 to PACR7

        176
    • 10.4. Operations of Memory Protection Function

      180
      • 10.4.1. Setting Up Memory Protection Areas

        181
      • 10.4.2. Instruction Access Protection Violation

        182
      • 10.4.3. Data Access Protection Violation

        183
      • 10.4.4. Data Access Errors

        184
      • 10.4.5. Memory Protection Operation by Delay Slot

        185
      • 10.4.6. DEAR and DESR Update

        186
      • 10.4.7. Notes

        187
• CHAPTER 4: OPERATION MODE

  189
  • 1. Overview

    190
  • 2. Features

    191
  • 3. Configuration

    192
  • 4. Register

    193
    • 4.1. Bus Mode Register : BMODR (Bus MODe Register)

      194
  • 5. Operation

    195
    • 5.1. MD0, MD1, P006 Pins Settings

      196
    • 5.2. Fetching the Operation Mode

      197
    • 5.3. Explanation of Each Operation Mode

      198
      • 5.3.1. User Mode

        199
      • 5.3.2. Serial Writer Mode

        200
• CHAPTER 5: CLOCK

  201
  • 1. Overview

    202
  • 2. Features

    204
  • 3. Configuration

    205
  • 4. Registers

    209
    • 4.1. Division Configuration Register 0 : DIVR0 (Division clock configuration Register 0)

      210
    • 4.2. Division Configuration Register 1 : DIVR1 (Division clock configuration Register 1)

      211
    • 4.3. Division Configuration Register 2 : DIVR2 (Division clock configuration Register 2)

      212
    • 4.4. Clock Source Selection Register : CSELR (Clock source Selection Register)

      213
    • 4.5. Clock Source Monitor Register : CMONR (Clock source MONitor Register)

      216
    • 4.6. Main Timer Control Register : MTMCR (Main clock TiMer Control Register)

      218
    • 4.7. Sub Timer Control Register : STMCR (Sub clock TiMer Control Register)

      220
    • 4.8. PLL Setting Register : PLLCR (PLL Configuration Register)

      222
    • 4.9. Clock Stabilization Selection Register : CSTBR (Clock STaBilization selection Register)

      225
    • 4.10. PLL Oscillation Timer Control Register : PTMCR (PLL clock osc TiMer Control Register)

      227
    • 4.11. PLL/SSCG Clock Selection Register : CCPSSELR (CCtl Pll/Sscg clock Selection Register)

      228
    • 4.12. PLL/SSCG Output Clock Division Setting Register : CCPSDIVR (CCtl Pll/Sscg clock DIVision Register)

      229
    • 4.13. PLL Feedback Division Setting Register : CCPLLFBR (CCtl PLL FB clock division Register)

      231
    • 4.14. SSCG Feedback Division Setting Register 0 : CCSSFBR0 (CCtl SScg FB clock division Register 0)

      232
    • 4.15. SSCG Feedback Division Setting Register 1 : CCSSFBR1 (CCtl SScg FB clock division Register 1)

      233
    • 4.16. SSCG Configuration Setting Register 0 : CCSSCCR0 (CCtl SSCg Config. Register 0)

      234
    • 4.17. SSCG Configuration Setting Register 1 : CCSSCCR1 (CCtl SSCg Config. Register 1)

      236
    • 4.18. Clock Gear Configuration Setting Register 0 : CCCGRCR0 (CCtl Clock Gear Config. Register 0)

      237
    • 4.19. Clock Gear Configuration Setting Register 1 : CCCGRCR1 (CCtl Clock Gear Config. Register 1)

      239
    • 4.20. Clock Gear Configuration Setting Register 2 : CCCGRCR2 (CCtl Clock Gear Config. Register 2)

      240
    • 4.21. RTC/PMU Clock Selection Register : CCRTSELR (CCtl RTc pmu clock Selection Register)

      241
    • 4.22. PMU Clock Division Setting Register 0 : CCPMUCR0 (CCtl PMU Clock division Register 0)

      243
    • 4.23. PMU Clock Division Setting Register 1 : CCPMUCR1 (CCtl PMU Clock division Register 1)

      244
    • 4.24. Sync/Async Control Register : SACR

      246
    • 4.25. Peripheral Interface Clock Divider : PICD

      247
  • 5. Operation

    249
    • 5.1. Oscillation Control

      250
      • 5.1.1. Main Clock (MCLK)

        251
      • 5.1.2. Sub Clock (SBCLK)

        252
      • 5.1.3. PLL/SSCG Clock (PLLSSCLK)

        253
      • 5.1.4. Limitations when PLL/SSCG Clock is used

        256
    • 5.2. Oscillation Stabilization Wait

      257
      • 5.2.1. Conditions for Generating Stabilization Wait Time

        258
      • 5.2.2. Selecting Stabilization Wait Time

        259
      • 5.2.3. End of the Stabilization Wait Time

        260
    • 5.3. Selecting the Source Clock (SRCCLK)

      261
      • 5.3.1. Selecting the Source Clock at the Time of Initialization

        262
      • 5.3.2. Procedure of switching the source clock

        263
    • 5.4. Timer

      268
      • 5.4.1. Main Clock Oscillation Stabilization Wait Timer (Main Timer)

        269
      • 5.4.2. Sub Clock Oscillation Stabilization Wait Timer (Sub Timer)

        270
      • 5.4.3. PLL/SSCG Clock Oscillation Stabilization Wait timer (PLL Timer)

        271
      • 5.4.4. Setting

        272
      • 5.4.5. Procedure for Setting the Timer Interrupt

        273
      • 5.4.6. Timer Operations

        274
      • 5.4.7. Watch Mode and Timer Interrupt

        275
    • 5.5. Notes when Clocks Conflict

      276
    • 5.6. The Clock Gear Circuit

      277
      • 5.6.1. Procedure of Gear Up

        278
      • 5.6.2. Procedure of Gear Down

        279
    • 5.7. Operations during MDI Communications

      280
    • 5.8. About PMU clock (PMUCLK)

      281
• CHAPTER 6: CLOCK RESET STATE TRANSITIONS

  283
  • 1. Overview

    284
  • 2. Device States and Transitions

    285
    • 2.1. Diagram of State Transitions

      286
    • 2.2. Explanation of Each States

      288
    • 2.3. Priority of State Transition Requests

      290
  • 3. Device State and Regulator Mode Corresponding to those States

    291
• CHAPTER 7: RESET

  293
  • 1. Overview

    294
  • 2. Features

    295
  • 3. Configuration

    296
  • 4. Registers

    298
    • 4.1. Reset Source Register : RSTRR (ReSeT Result Register)

      299
    • 4.2. Reset Control Register : RSTCR (ReSeT Control Register)

      301
    • 4.3. CPU Abnormal Operation Register : CPUAR (CPU Abnormal operation Register)

      302
    • 4.4. PMU Status Register : PMUSTR (Power Management Unit STatus register)

      304
  • 5. Operation

    305
    • 5.1. Reset Level

      306
      • 5.1.1. Initialize Reset (INIT)

        307
      • 5.1.2. Reset (RST)

        308
    • 5.2. Reset Factor

      309
      • 5.2.1. Power-on Reset

        310
      • 5.2.2. RSTX Pin Input

        311
      • 5.2.3. Watchdog Reset 0

        312
      • 5.2.4. Watchdog Reset 1

        313
      • 5.2.5. External Low-Voltage Detection Reset

        314
      • 5.2.6. Illegal Standby Mode Transition Detection Reset

        315
      • 5.2.7. Internal Low-Voltage Detection Reset

        316
      • 5.2.8. Flash Security Violation Reset

        317
      • 5.2.9. Software Reset (RSTCR:SRST)

        318
      • 5.2.10. Recovery from Standby (Power Interception)

        319
    • 5.3. Reset Acceptance

      320
      • 5.3.1. Generation of Reset Request

        321
      • 5.3.2. Acceptance of Reset Request

        322
      • 5.3.3. Reset Issue Delay Counter

        323
      • 5.3.4. Irregular Reset

        324
    • 5.4. Reset Issue

      325
      • 5.4.1. Super Initialize Reset (SINIT)

        326
      • 5.4.2. Initialize Reset (INIT)

        328
      • 5.4.3. Reset (RST)

        329
    • 5.5. Reset Sequence

      330
      • 5.5.1. Reset Cycle

        331
      • 5.5.2. Reset Release

        332
      • 5.5.3. Operating Mode Fix

        333
      • 5.5.4. Transition of Bus Control

        334
      • 5.5.5. Reset Vector Fetch

        335
      • 5.5.6. Reset and Forced Break

        336
    • 5.6. Notes

      337
• CHAPTER 8: DMA CONTROLLER (DMAC)

  339
  • 1. Overview

    340
  • 2. Features

    341
  • 3. Configuration

    342
  • 4. Registers

    343
    • 4.1. DMA Control Register: DMACR (DMA Control Register)

      346
    • 4.2. DMA Channel Control Register 0 to 15: DCCR0 to 15 (DMA Channel Control Register 0 to 15)

      348
    • 4.3. DMA Channel Status Register 0 to 15 : DCSR0 to 15: (DMA Channel Status Register 0 to 15)

      354
    • 4.4. DMA Transfer Count Register 0 to 15 : DTCR0 to 15: (DMA Transfer Count Register 0 to 15)

      356
    • 4.5. DMA Transfer Source Register 0 to 15 : DSAR0 to 15: (DMA Source Address Register 0 to 15)

      357
    • 4.6. DMA Transfer Destination Register 0 to 15 : DDAR0 to 15 (DMA Destination Address Register 0 to 15)

      358
    • 4.7. DMA Transfer Suppression NMI Flag Register : DNMIR (DMA-halt by NMI Register)

      359
    • 4.8. DMA Transfer Suppression Level Register : DILVR (DMA-halt by Interrupt Level Register)

      360
  • 5. Operation

    362
    • 5.1. Configuration

      363
      • 5.1.1. Common Items for All Channels

        364
      • 5.1.2. Separate Items for Each Channel

        365
      • 5.1.3. Operations

        369
  • 6. DMA Usage Examples

    382
• CHAPTER 9: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS

  385
  • 1. Overview

    386
  • 2. Features

    387
    • 2.1. Transfer Request Generation Setting

      388
    • 2.2. Interrupt Clearing Setting

      389
  • 3. Configuration

    390
  • 4. Registers

    391
    • 4.1. DMA Request Clear Register 0 : ICSEL0 (Interrupt Clear SELect register 0)

      393
    • 4.2. DMA Request Clear Register 1 : ICSEL1 (Interrupt Clear SELect register 1)

      394
    • 4.3. DMA Request Clear Register 2 : ICSEL2 (Interrupt Clear SELect register 2)

      395
    • 4.4. DMA Request Clear Register 3 : ICSEL3 (Interrupt Clear SELect register 3)

      396
    • 4.5. DMA Request Clear Register 5 : ICSEL5 (Interrupt Clear SELect register 5)

      397
    • 4.6. DMA Request Clear Register 6 : ICSEL6 (Interrupt Clear SELect register 6)

      398
    • 4.7. DMA Request Clear Register 7 : ICSEL7 (Interrupt Clear SELect register 7)

      399
    • 4.8. DMA Request Clear Register 8 : ICSEL8 (Interrupt Clear SELect register 8)

      400
    • 4.9. DMA Request Clear Register 9 : ICSEL9 (Interrupt Clear SELect register 9)

      401
    • 4.10. DMA Request Clear Register 10 : ICSEL10 (Interrupt Clear SELect register 10)

      402
    • 4.11. DMA Request Clear Register 11 : ICSEL11 (Interrupt Clear SELect register 11)

      403
    • 4.12. DMA Request Clear Register 13 : ICSEL13 (Interrupt Clear SELect register 13)

      404
    • 4.13. DMA Request Clear Register 14 : ICSEL14 (Interrupt Clear SELect register 14)

      405
    • 4.14. DMA Request Clear Register 15 : ICSEL15 (Interrupt Clear SELect register 15)

      406
    • 4.15. DMA Request Clear Register 16 : ICSEL16 (Interrupt Clear SELect register 16)

      407
    • 4.16. DMA Request Clear Register 17 : ICSEL17 (Interrupt Clear SELect register 17)

      408
    • 4.17. DMA Request Clear Register 18 : ICSEL18 (Interrupt Clear SELect register 18)

      409
    • 4.18. DMA Request Clear Register 19 : ICSEL19 (Interrupt Clear SELect register 19)

      410
    • 4.19. DMA Request Clear Register 20 : ICSEL20 (Interrupt Clear SELect register 20)

      411
    • 4.20. DMA Request Clear Register 21 : ICSEL21 (Interrupt Clear SELect register 21)

      412
    • 4.21. DMA Request Clear Register 22 : ICSEL22 (Interrupt Clear SELect register 22)

      413
    • 4.22. DMA Request Clear Register 23 : ICSEL23 (Interrupt Clear SELect register 23)

      414
    • 4.23. DMA Request Clear Register 24 : ICSEL24 (Interrupt Clear SELect register 24)

      415
    • 4.24. DMA Request Clear Register 25 : ICSEL25 (Interrupt Clear SELect register 25)

      416
    • 4.25. DMA Request Clear Register 26 : ICSEL26 (Interrupt Clear SELect register 26)

      418
    • 4.26. DMA Request Clear Register 27 : ICSEL27 (Interrupt Clear SELect register 27)

      419
    • 4.27. IO Transfer Request Setting Register 0 to 15 : IORR0 to 15 (IO triggered DMA Request Register for ch. 0 to 15)

      420
  • 5. Operation

    422
    • 5.1. Configuration

      423
    • 5.2. Notes

      424
• CHAPTER 10: FIXEDVECTOR FUNCTION

  425
  • 1. Overview

    426
  • 2. Features

    427
  • 3. Configuration

    428
  • 4. Registers

    429
  • 5. Operation

    430
    • 5.1. Operation After Reset Released

      431
    • 5.2. Usage

      432
  • 6. Notes

    433
• CHAPTER 11: I/O PORTS

  435
  • 1. Overview

    436
  • 2. Features

    437
  • 3. Configuration

    438
  • 4. Registers

    439
    • 4.1. Port Data Register 00 to 19 : PDR00 to 19 (Port Data Register 00 to 19)

      442
    • 4.2. Data Direction Register 00 to 19 : DDR00 to 19 (Data Direction Register 00 to 19)

      443
    • 4.3. Port Function Register 00 to 19 : PFR00 to 19 (Port Function Register 00 to 19)

      444
    • 4.4. Input Data Direct Register 00 to 19 : PDDR00 to 19 (Port Data Direct Register 00 to 19)

      445
    • 4.5. Port Pull-up/down Enable Register 00 to 19 : PPER00 to 19 (Port Pull-up/down Enable Register 00 to 19)

      446
    • 4.6. Extended Port Function Register 00 to 88 : EPFR00 to 88 (Extended Port Function Register 00 to 88)

      447
      • 4.6.1. Extended Port Function Register 00, 01, 56 : EPFR00, EPFR01, EPFR56

        448
      • 4.6.2. Extended Port Function Register 02 to 05, 57 to 60 : EPFR02 to 05, 57 to 60

        450
      • 4.6.3. Extended Port Function Register 06 to 09, 33 to 36, 61 to 64 : EPFR06 to 09, 33 to 36, 61 to 64

        453
      • 4.6.4. Extended Port Function Register 10 to 15, 45, 71 to 78 : EPFR10 to 15, 45, 71 to 78

        457
      • 4.6.5. Extended Port Function Register 79, 80 : EPFR79, 80

        461
      • 4.6.6. Extended Port Function Register 86 : EPFR86

        462
      • 4.6.7. Extended Port Function Register 26 : EPFR26

        463
      • 4.6.8. Extended Port Function Register 27 : EPFR27

        464
      • 4.6.9. Extended Port Function Register 28 : EPFR28

        465
      • 4.6.10. Extended Port Function Register 29, 81, 82 : EPFR29, 81, 82

        466
      • 4.6.11. Extended Port Function Register 83 : EPFR83

        467
      • 4.6.12. Extended Port Function Register 42 : EPFR42

        468
      • 4.6.13. Extended Port Function Register 43, 44 : EPFR43, 44

        469
      • 4.6.14. Extended Port Function Register 48 to 51 : EPFR48 to 51

        470
      • 4.6.15. Extended Port Function Register 65 to 70 : EPFR65 to 70

        471
      • 4.6.16. Extended Port Function Register 84, 85 : EPFR84, 85

        474
      • 4.6.17. Extended Port Function Register 87 : EPFR87

        475
      • 4.6.18. Extended Port Function Register 88 : EPFR88

        476
    • 4.7. Port Input Enable Register: PORTEN (PORT ENable register)

      477
    • 4.8. KEY CoDe Register : KEYCDR

      478
  • 5. Operation

    480
    • 5.1. Pin I/O Assignment

      481
      • 5.1.1. Peripheral I/O (bidirectional) Pin Assignment

        482
      • 5.1.2. Peripheral Input Assignment

        483
      • 5.1.3. Peripheral Output Assignment

        485
      • 5.1.4. External Bus Assignment

        486
      • 5.1.5. Port Function (Input) Assignment

        487
      • 5.1.6. Port Function (Output) Assignment

        488
      • 5.1.7. AD Converter Input Assignment

        489
      • 5.1.8. DA converter output assignment

        490
    • 5.2. EPFR setting priority

      491
    • 5.3. Notes on Input I/O Relocation Setting

      492
    • 5.4. Noise Filter

      493
    • 5.5. Input blocked by GPORTEN

      494
    • 5.6. Notes on Pins with the AD Converter Function

      495
    • 5.7. Setting when Using the Base Timer TIOA1 Pin

      496
    • 5.8. Key Code Register Function Settings

      497
    • 5.9. Operation at Wake Up from Power Shutdown

      498
    • 5.10. Notes on switching the I/O port function

      499
• CHAPTER 12: INTERRUPT CONTROL (INTERRUPT CONTROLLER)

  501
  • 1. Overview

    502
  • 2. Features

    503
  • 3. Configuration

    504
  • 4. Registers

    505
    • 4.1. Interrupt Control Registers 00 to 47 : ICR00 to ICR47 (Interrupt Control Register 00 to 47):

      506
  • 5. Operation

    507
    • 5.1. Setup

      508
    • 5.2. Starting

      509
    • 5.3. Determining Priorities

      510
    • 5.4. Recovering From Stop Mode

      511
    • 5.5. Recovering From Standby Mode (Power shutdown)

      512
• CHAPTER 13: EXTERNAL INTERRUPT INPUT

  513
  • 1. Overview

    514
  • 2. Features

    515
  • 3. Configuration

    516
  • 4. Registers

    517
    • 4.1. External Interrupt Factor Register 0/1 : EIRR0/EIRR1 (External Interrupt Request Register 0/1)

      518
    • 4.2. External Interrupt Enable Register 0/1 : ENIR0/ENIR1 (ENable Interrupt request Register 0/1)

      519
    • 4.3. External Interrupt Request Level Register 0/1 : ELVR0/ELVR1 (External interrupt LeVel Register 0/1)

      520
  • 5. Operation

    521
  • 6. Setting

    523
  • 7. Q&A

    524
  • 8. Notes

    525
• CHAPTER 14: NMI INPUT

  527
  • 1. Overview

    528
  • 2. Features

    529
  • 3. Configuration

    530
  • 4. Register

    531
  • 5. Operation

    532
  • 6. Usage Example

    533
• CHAPTER 15: DELAY INTERRUPT

  535
  • 1. Overview

    536
  • 2. Features

    537
  • 3. Configuration

    538
  • 4. Registers

    539
  • 5. Operation

    540
  • 6. Restrictions

    541
• CHAPTER 16: INTERRUPT REQUEST BATCH READ

  543
  • 1. Overview

    544
  • 2. Features

    545
  • 3. Configuration

    546
  • 4. Registers

    547
    • 4.1. Interrupt Request Batch Read Register 0 upper-order : IRPR0H (Interrupt Request Peripheral Read register 0H)

      549
    • 4.2. Interrupt Request Batch Read Register 0 lower-order : IRPR0L (Interrupt Request Peripheral Read register 0L)

      550
    • 4.3. Interrupt Request Batch Read Register 1 upper-order : IRPR1H (Interrupt Request Peripheral Read register 1H)

      551
    • 4.4. Interrupt Request Batch Read Register 1 lower-order : IRPR1L (Interrupt Request Peripheral Read register 1L)

      552
    • 4.5. Interrupt Request Batch Read Register 3 upper-order : IRPR3H (Interrupt Request Peripheral Read register 3H)

      553
    • 4.6. Interrupt Request Batch Read Register 3 lower-order : IRPR3L (Interrupt Request Peripheral Read register 3L)

      554
    • 4.7. Interrupt Request Batch Read Register 4 upper-order : IRPR4H (Interrupt Request Peripheral Read register 4H)

      555
    • 4.8. Interrupt Request Batch Read Register 4 lower-order : IRPR4L (Interrupt Request Peripheral Read register 4L)

      556
    • 4.9. Interrupt Request Batch Read Register 5 upper-order : IRPR5H (Interrupt Request Peripheral Read register 5H)

      557
    • 4.10. Interrupt Request Batch Read Register 5 lower-order : IRPR5L (Interrupt Request Peripheral Read register 5L)

      558
    • 4.11. Interrupt Request Batch Read Register 6 upper-order : IRPR6H (Interrupt Request Peripheral Read register 6H)

      559
    • 4.12. Interrupt Request Batch Read Register 6 lower-order : IRPR6L (Interrupt Request Peripheral Read register 6L)

      560
    • 4.13. Interrupt Request Batch Read Register 7 upper-order : IRPR7H (Interrupt Request Peripheral Read register 7H)

      561
    • 4.14. Interrupt Request Batch Read Register 7 lower-order : IRPR7L (Interrupt Request Peripheral Read register 7L)

      562
    • 4.15. Interrupt Request Batch Read Register 8 upper-order IRPR8H (Interrupt Request Peripheral Read register 8H)

      563
    • 4.16. Interrupt Request Batch Read Register 8 lower-order : IRPR8L (Interrupt Request Peripheral Read register 8L)

      564
    • 4.17. Interrupt Request Batch Read Register 9 upper-order : IRPR9H (Interrupt Request Peripheral Read register 9H)

      565
    • 4.18. Interrupt Request Batch Read Register 9 lower-order : IRPR9L (Interrupt Request Peripheral Read register 9L)

      566
    • 4.19. Interrupt Request Batch Read Register 10 upper-order : IRPR10H (Interrupt Request Peripheral Read register 10H)

      567
    • 4.20. Interrupt Request Batch Read Register 10 lower-order : IRPR10L (Interrupt Request Peripheral Read register 10L)

      568
    • 4.21. Interrupt Request Batch Read Register 11 upper-order : IRPR11H (Interrupt Request Peripheral Read register 11H)

      569
    • 4.22. Interrupt Request Batch Read Register 11 lower-order : IRPR11L (Interrupt Request Peripheral Read register 11L)

      570
    • 4.23. Interrupt Request Batch Read Register 12 upper-order : IRPR12H (Interrupt Request Peripheral Read register 12H)

      571
    • 4.24. Interrupt Request Batch Read Register 12 lower-order : IRPR12L (Interrupt Request Peripheral Read register 12L)

      572
    • 4.25. Interrupt Request Batch Read Register 13 upper-order : IRPR13H (Interrupt Request Peripheral Read register 13H)

      573
    • 4.26. Interrupt Request Batch Read Register 13 lower-order : IRPR13L (Interrupt Request Peripheral Read register 13L)

      574
    • 4.27. Interrupt Request Batch Read Register 14 upper-order : IRPR14H (Interrupt Request Peripheral Read register 14H)

      575
    • 4.28. Interrupt Request Batch Read Register 14 lower-order : IRPR14L (Interrupt Request Peripheral Read register 14L)

      576
    • 4.29. Interrupt Request Batch Read Register 15 upper-order : IRPR15H (Interrupt Request Peripheral Read register 15H)

      577
    • 4.30. Interrupt Request Batch Read Register 15 lower-order : IRPR15L (Interrupt Request Peripheral Read register 15L)

      578
  • 5. Operation

    579
• CHAPTER 17: PPG

  581
  • 1. Overview

    582
  • 2. Features

    583
  • 3. Configuration

    587
  • 4. Registers

    588
    • 4.1. PPG Control Status Register : PCN0 to PCN 47

      595
    • 4.2. PPG Cycle Setting Register : PCSR0 to PCSR47

      599
    • 4.3. PPG Duty Setting Register : PDUT0 to PDUT47

      600
    • 4.4. PPG Timer Register : PTMR0 to PTMR47

      601
    • 4.5. PPG Control Status Register2 : PCN200 to PCN247

      602
    • 4.6. Start Delay Value Setting Register : PSDR0 to PSDR47

      604
    • 4.7. Timing Point Capture Value Setting Register : PTPC0 to PTPC47

      605
    • 4.8. PPG Communication Mode High Format Cycle Setting Register : PHCSR0 to PHCSR3

      606
    • 4.9. PPG Communication Mode Low Format Cycle Setting Register : PLCSR0 to PLCSR3

      607
    • 4.10. PPG Communication Mode High Format Duty Setting Register : PHDUT0 to PHDUT3

      608
    • 4.11. PPG Communication Mode Low Format Duty Setting Register : PLDUT0 to PLDUT3

      609
    • 4.12. PPG Communication Mode Data Setting Register : PCMDDT0 to PCMDDT3

      610
    • 4.13. PPG Communication Mode Data Bit Length Setting Register : PCMDWD0 to PCMDWD3

      611
    • 4.14. GATE Function Control Register : GATEC0, GATEC2, GATEC4

      612
    • 4.15. General-purpose Trigger Selection Register : GTRS0 to GTRS23

      613
    • 4.16. General-purpose Trigger Setting Register : GTREN0 to GTREN2

      616
  • 5. Operation

    618
    • 5.1. PWM Operation (Normal Wave Form)

      619
    • 5.2. PWM Operation (Center Aligned Wave Form Selected)

      621
    • 5.3. One-shot Operation (Normal Wave Form Selected)

      623
    • 5.4. One-shot Operation (Center Aligned Wave Form Selected)

      625
    • 5.5. Restart Operation

      627
    • 5.6. GATE Operation

      628
    • 5.7. Start Delay Mode Operation (PWM Normal Wave Form Selected)

      629
    • 5.8. Timing Point Capture Mode Operation (PWM Normal Wave Form Selected)

      631
    • 5.9. PPG Communication Mode Operation

      633
    • 5.10. PPG Communication Activation

      634
    • 5.11. PPG Communication Operation

      635
    • 5.12. PPG Communication Forced Stop and Restart operation

      639
    • 5.13. PPG Output Pulse Polarity Selection

      641
    • 5.14. Interrupt

      643
  • 6. Notes

    644
• CHAPTER 18: WATCHDOG TIMER

  649
  • 1. Overview

    650
  • 2. Features

    651
    • 2.1. Watchdog Timer 0 (Software Watchdog)

      652
    • 2.2. Watchdog Timer 1 (Hardware Watchdog)

      653
  • 3. Configuration

    654
  • 4. Registers

    655
    • 4.1. Watchdog Control Register 0 : WDTCR0 (WatchDog Timer Configuration Register 0)

      656
    • 4.2. Watchdog Timer 0 Clear Register : WDTCPR0 (WatchDog Timer Clear Pattern Register 0)

      658
    • 4.3. Watchdog Timer 0 Extended Configuration Register : WDTECR0 (Watchdog Timer Extended Configuration Register 0)

      659
    • 4.4. Watchdog Timer 1 Cycle information Register : WDTCR1 (WatchDog Timer Cycle information Register 1)

      661
    • 4.5. Watchdog Timer 1 Clear Register : WDTCPR1 (WatchDog Timer Clear Pattern Register 1)

      662
  • 5. Operation

    663
    • 5.1. Software Watchdog Function

      664
      • 5.1.1. Settings

        665
      • 5.1.2. Activation

        666
      • 5.1.3. Operation

        667
    • 5.2. Hardware Watchdog Function

      668
      • 5.2.1. Settings

        669
      • 5.2.2. Activation

        670
      • 5.2.3. Operation

        671
  • 6. Usage Example

    672
• CHAPTER 19: BASE TIMER

  673
  • 1. Overview

    674
  • 2. Features

    675
    • 2.1. 16/32-bit Reload Timer

      676
    • 2.2. 16-bit PWM Timer

      677
    • 2.3. 16/32-bit PWC Timer

      678
    • 2.4. 16-bit PPG Timer

      679
  • 3. Configuration

    680
  • 4. Registers

    681
    • 4.1. Common Registers

      683
      • 4.1.1. Timer Registers 0, 1 : BTxTMR (Base Timer 0/1 TiMer Register)

        684
      • 4.1.2. Timer Control Registers 0, 1 : BTxTMCR (Base Timer 0/1 TiMer Control Register)

        685
      • 4.1.3. I/O Selection Register : BTSEL01 (Base Timer SElect register ch.0 and ch.1)

        691
      • 4.1.4. Simultaneous Software Activation Register : BTSSSR (Base Timer Software Synchronous Start Register)

        692
    • 4.2. Registers for 16/32-bit Reload Timer

      693
      • 4.2.1. Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control)

        694
      • 4.2.2. Cycle Setting Registers 0, 1 : BTxPCSR (Base Timer 0/1 Pulse Counter Start Register)

        695
    • 4.3. Registers for 16-bit PWM Timer

      696
      • 4.3.1. Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control)

        697
      • 4.3.2. Cycle Setting Registers 0, 1 : BTxPCSR (Base Timer 0/1 Pulse Counter Start Register)

        699
      • 4.3.3. Duty Setting Registers 0, 1 : BTxPDUT (Base Timer 0/1 Pulse DuTy register)

        700
    • 4.4. Registers for 16-bit PPG Timer

      701
      • 4.4.1. Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control)

        702
      • 4.4.2. L Width Setting Registers 0, 1 : BTxPRLL (Base Timer 0/1 Pulse Length of "L" register)

        703
      • 4.4.3. H Width Setting Registers 0, 1 : BTxPRLH (Base Timer 0/1 Pulse Length of "H" register)

        704
    • 4.5. 16/32-bit PWC Timer Register

      705
      • 4.5.1. Status Control Registers 0, 1 : BTxSTC (Base Timer 0/1 STatus Control)

        706
      • 4.5.2. Data Buffer Registers 0, 1 : BTxDTBF (Base Timer 0/1 DaTa BuFfer register)

        708
  • 5. Operation

    709
    • 5.1. Selection of Timer Function

      710
    • 5.2. I/O Allocation

      711
    • 5.3. 32-bit Mode Operation

      714
      • 5.3.1. 32-bit Mode Function

        715
      • 5.3.2. 32-bit Mode Setting

        716
      • 5.3.3. 32-bit Mode Operation

        717
    • 5.4. 16/32-bit Reload Timer Operation

      718
      • 5.4.1. Overview

        720
      • 5.4.2. Operation in Reload Mode

        721
      • 5.4.3. Operation in One-Shot Mode

        724
      • 5.4.4. 32-bit Timer Mode Operation

        726
      • 5.4.5. Interrupts

        728
      • 5.4.6. Precautions for Using this Device

        729
    • 5.5. 16-bit PWM Timer Operation

      730
      • 5.5.1. Overview

        731
      • 5.5.2. Operation in Reload Mode

        732
      • 5.5.3. Operation in One-Shot Mode

        736
      • 5.5.4. Interrupt

        738
      • 5.5.5. Precautions for Using this Device

        739
    • 5.6. 16-bit PPG Timer Operation

      740
      • 5.6.1. Overview

        741
      • 5.6.2. Pulse Width Calculation Method

        742
      • 5.6.3. Operation in Reload Mode

        743
      • 5.6.4. Operation in One-Shot Mode

        747
      • 5.6.5. Interrupts

        750
      • 5.6.6. Application Notes

        751
    • 5.7. 16/32-bit PWC Timer Operation

      752
      • 5.7.1. Overview

        754
      • 5.7.2. Operation during PWC Measurement

        759
      • 5.7.3. 32-bit Timer Mode Operation

        762
      • 5.7.4. Interrupt

        764
      • 5.7.5. Application Notes

        765
• CHAPTER 20: RELOAD TIMER

  767
  • 1. Overview

    768
  • 2. Features

    769
  • 3. Configuration

    770
  • 4. Registers

    771
    • 4.1. Control Status Register : TMCSR (TiMer Control and Status Register)

      773
    • 4.2. 16-bit Timer Register : TMR (16bit TiMer Register)

      777
    • 4.3. 16-bit Timer Reload Register A, 16-bit Timer Reload Register B : TMRLRA, TMRLRB(16bit TiMer ReLoad Register A/B)

      778
  • 5. Operation

    780
    • 5.1. Setting

      781
      • 5.1.1. Count Source

        782
      • 5.1.2. Timer Underflow period

        783
      • 5.1.3. Trigger

        784
      • 5.1.4. Gate

        785
      • 5.1.5. Counter Operation Selection

        786
      • 5.1.6. TOUT Pin Level Setting

        787
    • 5.2. Operation Procedure

      789
      • 5.2.1. Activation

        790
      • 5.2.2. Retrigger

        792
      • 5.2.3. Underflow/Reload

        794
      • 5.2.4. Generation of Interrupt Requests

        795
      • 5.2.5. Concurrent Operation of Register Write and a Timer Activation

        796
    • 5.3. Operations of Each Counter

      797
      • 5.3.1. Single One-shot Operation

        798
      • 5.3.2. Single Reload Operation

        800
      • 5.3.3. Dual One-shot Operation

        802
      • 5.3.4. Dual Reload Operation

        804
      • 5.3.5. Compare One-shot Operation

        806
      • 5.3.6. Compare Reload Operation

        809
      • 5.3.7. Capture Mode

        812
    • 5.4. Cascade Input

      815
    • 5.5. Priority of Concurrent Operations

      816
  • 6. Application Note

    817
    • 6.1. Single One-shot Timer

      819
    • 6.2. Reload Timer

      822
    • 6.3. PPG

      825
    • 6.4. PWM

      829
    • 6.5. PWC

      832
• CHAPTER 21: 32-BIT FREE-RUN TIMER

  835
  • 1. Overview

    836
  • 2. Features

    837
    • 2.1. Functions of the 32-bit free-run timer

      838
    • 2.2. Functions of the free-run timer selector

      839
  • 3. Configuration

    840
    • 3.1. Configuration diagram of the 32-bit free-run timer

      841
    • 3.2. Configuration diagram of the free-run timer selector

      842
  • 4. Registers

    843
    • 4.1. Registers of the 32-bit free-run timer

      844
      • 4.1.1. Timer Control Register (Upper Bit) : TCCSH

        845
      • 4.1.2. Timer Control Register (Lower Bit) : TCCSL

        847
      • 4.1.3. Compare Clear Register : CPCLR

        849
      • 4.1.4. Timer Data Register : TCDT

        850
    • 4.2. Registers of the free-run timer selector

      851
      • 4.2.1. Free-run timer selection register : FRS

        852
  • 5. Operation

    858
    • 5.1. Operation of the 32-bit free-run timer

      859
      • 5.1.1. Count Operation

        860
      • 5.1.2. Counting Up

        861
      • 5.1.3. Timer Clear

        862
      • 5.1.4. Each Clear Operations of the Free-run Timer

        863
      • 5.1.5. Timer Interrupt

        864
    • 5.2. Operation of the 32-bit free-run timer selector

      865
  • 6. Setting

    866
  • 7. Q&A

    867
    • 7.1. How to Select Internal Clock Dividers?

      868
    • 7.2. How to Select the External Clock?

      869
    • 7.3. How to Enable/Disable the Count Operation of the Free-run Timer?

      870
    • 7.4. How to Clear the Free-run Timer?

      871
    • 7.5. About Interrupt Related Registers?

      872
    • 7.6. How to Enable Compare Clear Interrupt?

      873
    • 7.7. How to Stop the Free-run Timer Operation?

      874
  • 8. Sample Program

    875
  • 9. Notes

    876
• CHAPTER 22: 32-BIT OUTPUT COMPARE

  877
  • 1. Overview

    878
  • 2. Features

    879
  • 3. Configuration Diagram

    881
  • 4. Registers

    882
    • 4.1. Output Control Register (Upper Bit) : OCSH

      883
    • 4.2. Output Control Register (Lower Bit) : OCSL

      885
    • 4.3. Compare Register : OCCP

      887
    • 4.4. Output Level Control Register : OCLS

      888
  • 5. Operation

    889
    • 5.1. Output Compare Output (Independent Invert) CMOD = "0"

      890
    • 5.2. Output Compare Output (Coordinated Invert) CMOD = "1"

      891
    • 5.3. Output Compare Operation Timing

      892
      • 5.3.1. Compare Register Write

        893
      • 5.3.2. Compare match, Interrupt

        894
      • 5.3.3. Pin Output

        895
  • 6. Setting

    896
  • 7. Q&A

    897
    • 7.1. How Can I Set the Compare Value?

      898
    • 7.2. How Can I Set the Compare Mode? (Example with OCU7)

      899
    • 7.3. How Can I Enable/Disable the Compare Operation? (Example with OCU6,7)

      900
    • 7.4. How Can I Set the Compare Pin Output Initial Level? (Example with OCU6,7)

      901
    • 7.5. How Can I Set the Compare Pin OCU6-OCU7 for Output?

      902
    • 7.6. How Can I Clear the Free-run Timer?

      903
    • 7.7. How Can I Enable the Compare Operation? (Example with OCU6,7)

      904
    • 7.8. Interrupt Related Register?

      905
    • 7.9. Interrupt Type?

      906
    • 7.10. How Can I Enable the Interrupt?

      907
    • 7.11. Calculation Method for the Compare Value?

      908
      • 7.11.1. Toggle Output Pulse

        909
      • 7.11.2. PWM Output

        910
    • 7.12. To Set the Operation Mode?

      911
  • 8. Sample Program

    912
  • 9. Notes

    914
• CHAPTER 23: 32-BIT INPUT CAPTURE

  915
  • 1. Overview

    916
  • 2. Features

    917
  • 3. Configuration

    918
  • 4. Registers

    919
    • 4.1. Input Capture Data Register : IPCP

      921
    • 4.2. Input Capture Control Register : ICS

      922
    • 4.3. LIN SYNCH FIELD Switching Register : LSYNS

      923
    • 4.4. Cycle Measurement Data Register : MSCY

      924
    • 4.5. Cycle and Pulse Width Measurement Control Register (Upper bit) : MSCH

      925
    • 4.6. Cycle and Pulse Width Measurement Control Register (Lower bit) : MSCL

      927
  • 5. Operation

    928
    • 5.1. Capture and Interrupt Timings

      929
    • 5.2. Edge Detection Specifications for Input Capture And Their Operations

      930
    • 5.3. Cycle and Pulse Width Measurement Operation

      932
  • 6. Setting

    936
  • 7. Q&A

    937
    • 7.1. Effective Edge Polarity of External Input: Types and How to Select?

      938
    • 7.2. How to Enable External Input Pins (ICU4 to ICU9)?

      939
    • 7.3. About Interrupt Related Registers

      940
    • 7.4. About Interrupt Types

      941
    • 7.5. How to Enable Interrupt?

      942
    • 7.6. How to Measure the Pulse Width of the Input Signal?

      943
    • 7.7. How to Set the Setting of the Operation Mode?

      944
  • 8. Sample Program

    945
  • 9. Notes

    946
• CHAPTER 24: 16-BIT FREE-RUN TIMER

  947
  • 1. Overview

    948
  • 2. Features

    949
  • 3. Configuration

    950
  • 4. Registers

    953
    • 4.1. Registers for the Free-run Timer Simultaneous Activation

      954
      • 4.1.1. Timer Synchronous Activation Register : (TCGS)

        954
      • 4.1.2. Timer Synchronous Activation Enable Register : TCGSE

        956
    • 4.2. Registers for the 16-bit Free-run Timer

      957
      • 4.2.1. Compare Clear Buffer Register : CPCLRB/ Compare Clear Register : CPCLR

        957
      • 4.2.2. Timer Data Register : TCDT0 to TCDT2

        959
      • 4.2.3. Timer State Control Register : TCCS0 to TCCS2

        961
    • 4.3. Register for the Free-run Timer Selector

      969
      • 4.3.1. Free-run Timer Selection Register : FRS

        969
  • 5. Operation

    981
    • 5.1. Interrupt for the 16-bit Free-run Timer

      982
    • 5.2. Operation of the 16-bit Free-run Timer

      983
      • 5.2.1. Timer Clear

        983
      • 5.2.2. Timer Mode

        984
      • 5.2.3. Compare Clear Buffer

        985
      • 5.2.4. Timer Interrupt

        987
      • 5.2.5. Interrupt Mask Function

        988
      • 5.2.6. Selected External Count Clock

        990
    • 5.3. Operation of the Free-run Timer Selector

      991
    • 5.4. Notes on Operating Specifications

      993
      • 5.4.1. Notes at Accessing the Buffer Registers

        993
      • 5.4.2. Notes on Using the 16-bit Free-run Timer

        993
      • 5.4.3. Notes on Using the Free-run Timer Selector

        994
• CHAPTER 25: 16-BIT OUTPUT COMPARE

  995
  • 1. Overview

    996
  • 2. Features

    997
  • 3. Configuration Diagram

    998
  • 4. Registers

    999
    • 4.1. 16-bit Output Compare Registers

      1000
      • 4.1.1. Output Compare Buffer Registers (OCCPB0 to OCCPB5)/Output Compare Registers (OCCP0 to OCCP5)

        1001
      • 4.1.2. Compare Control Register (OCS)

        1005
      • 4.1.3. Compare Mode Control Register (OCMOD)

        1011
  • 5. Operation

    1013
    • 5.1. Interrupts for 16-bit Output Compare

      1014
    • 5.2. Operation of 16-bit Output Compare

      1015
      • 5.2.1. Operation of 16-bit Output Compare (Inverted Mode, MOD0= 0 in OCMOD01 Register)

        1016
      • 5.2.2. Operation of 16-bit Output Compare (Set/Reset Mode, MOD0 = 1 in OCMOD01 Register)

        1019
      • 5.2.3. 16-bit Output Compare Timing

        1020
      • 5.2.4. Operation of 16-bit Output Compare and Free-run Timer

        1021
    • 5.3. Notes on Using 16-bit Output Compare

      1028
• CHAPTER 26: 16-BIT INPUT CAPTURE

  1029
  • 1. Overview

    1030
  • 2. Features

    1031
  • 3. Configuration

    1032
  • 4. Registers

    1033
    • 4.1. 16-bit Input Capture Registers

      1034
      • 4.1.1. Input Capture Data Register : IPCP0 to IPCP3

        1035
      • 4.1.2. Input Capture State Control Register : ICS

        1036
      • 4.1.3. LIN SYNCH FIELD Switching Register : LSYNS

        1039
  • 5. Operation

    1040
    • 5.1. Interrupts for 16-bit Input Capture

      1041
    • 5.2. Operation of 16-bit Input Capture

      1042
      • 5.2.1. Operation of 16-bit Input Capture

        1043
      • 5.2.2. 16-bit Input Capture Input Timing

        1044
    • 5.3. Notes on Using the 16-bit Input Capture

      1045
• CHAPTER 27: UP/DOWN COUNTER

  1047
  • 1. Overview

    1048
  • 2. Features

    1049
  • 3. Configuration

    1051
  • 4. Registers

    1053
    • 4.1. Reload Compare Register (RCR0, RCR1)

      1054
    • 4.2. Up/Down Count Register (UDCR0, UDCR1)

      1055
    • 4.3. Counter Control Register (CCR0, CCR1)

      1056
    • 4.4. Counter Status Register (CSR0, CSR1)

      1061
  • 5. Interrupt

    1064
  • 6. Operation and Setting Procedure Examples

    1066
    • 6.1. Operation in Timer Mode

      1070
    • 6.2. Operation in Up/down Count Mode

      1072
    • 6.3. Operation in the Phase Difference Count Mode (Multiply-by-Two)

      1075
    • 6.4. Operation in the Phase Difference Count Mode (Multiply-by-Four)

      1077
• CHAPTER 28: REAL-TIME CLOCK(RTC)

  1079
  • 1. Overview

    1080
  • 2. Features

    1081
  • 3. Configuration

    1082
  • 4. Registers

    1083
    • 4.1. RTC Control Register : WTCR

      1084
    • 4.2. Sub-second Register : WTBR

      1088
    • 4.3. Day/Hour/Minute/Second Register : WTDR/ WTHR/ WTMR/ WTSR

      1090
  • 5. Operation

    1092
  • 6. Setting

    1094
  • 7. Q&A

    1095
    • 7.1. How to Set the 0.5 Second Count Interval?

      1096
    • 7.2. How to Initialize the Real-time Clock?

      1097
    • 7.3. How to Set/Update Number of Days (Day) and Time (Hour/Minute/Second)?

      1098
    • 7.4. How to Start/Stop the Count of the Real-time Clock?

      1099
    • 7.5. How to Confirm That the Real-time Clock Is Running?

      1100
    • 7.6. How to Know the Number of Days and Time?

      1101
    • 7.7. How to Stop the Real-time Clock?

      1102
    • 7.8. How to Calibrate the Real-time Clock?

      1103
    • 7.9. What Are Interrupt Related Registers?

      1104
    • 7.10. What Are the Interrupt Types and How to Select Them?

      1105
    • 7.11. How to Enable Interrupts?

      1106
  • 8. Sample Program

    1107
  • 9. Notes

    1108
• CHAPTER 29: RTC/WDT1 CALIBRATION

  1109
  • 1. Overview

    1110
  • 2. Features

    1111
  • 3. Configuration

    1112
  • 4. Registers

    1113
    • 4.1. Calibration Unit Control Register 0 : CUCR0 (Calibration Unit Control Register 0)

      1114
    • 4.2. Sub Clock Timer Data Register : CUTD0 (Calibration Unit Timer Data register 0)

      1116
    • 4.3. Main Oscillation Timer Result Register 0 : CUTR0 (Calibration Unit Timer Result register 0)

      1117
    • 4.4. Calibration Unit Control Register 1 : CUCR1 (Calibration Unit Control Register 1)

      1118
    • 4.5. CR Clock Timer Data Register : CUTD1 (Calibration Unit Timer Data register 1)

      1120
    • 4.6. Main Oscillation Timer Result Register 1 : CUTR1 (Calibration Unit Timer Result register 1)

      1121
  • 5. Operation

    1122
    • 5.1. Real-Time Clock (RTC) Calibration

      1123
    • 5.2. Measurement of Errors in CR Clock

      1124
    • 5.3. Note

      1125
• CHAPTER 30: POWER CONSUMPTION CONTROL

  1127
  • 1. Overview

    1128
  • 2. Features

    1129
  • 3. Configuration

    1130
  • 4. Registers

    1132
    • 4.1. Standby Control Register: STBCR (STandby mode Control Register)

      1133
    • 4.2. PMU Control Register : PMUCTLR (Power Management Unit ConTroL register)

      1135
    • 4.3. PoWeR on TiMing Control Register : PWRTMCTL (PoWeR on TiMing ConTroL register)

      1136
    • 4.4. PMU Interrupt Flag Register 0 : PMUINTF0 (Power Management Unit INTerrupt Flag0 register)

      1137
    • 4.5. PMU Interrupt Flag Register 1 : PMUINTF1 (Power Management Unit INTerrupt Flag1 register)

      1138
    • 4.6. PMU Interrupt Flag Register 2 : PMUINTF2 (Power Management Unit INTerrupt Flag2 register)

      1139
  • 5. Operation

    1140
    • 5.1. Clock Control

      1141
      • 5.1.1. Division Setting

        1142
      • 5.1.2. Stopping of Unused Clocks

        1143
    • 5.2. List of Clocks Supplied in Low-power Consumption Mode

      1144
    • 5.3. Sleep Mode

      1145
      • 5.3.1. CPU Sleep Mode

        1146
      • 5.3.2. Bus Sleep Mode

        1147
      • 5.3.3. Configuration of Sleep Mode

        1148
      • 5.3.4. Activation of Sleep mode

        1149
      • 5.3.5. Wake Up from the Sleep Mode

        1150
      • 5.3.6. Effect of Sleep Mode

        1151
    • 5.4. Standby Mode : Watch Mode

      1152
      • 5.4.1. Configuration of Watch Mode

        1153
      • 5.4.2. Activation of Watch Mode

        1154
      • 5.4.3. Wake Up from the Watch Mode

        1155
      • 5.4.4. Effect of Watch Mode

        1156
    • 5.5. Standby Mode : Watch Mode with power-shutdown

      1157
      • 5.5.1. Configuration of Watch Mode with power-shutdown

        1158
      • 5.5.2. Activation of Watch Mode with power-shutdown

        1159
      • 5.5.3. Wake Up from the Watch Mode with power-shutdown

        1161
      • 5.5.4. Effect of Watch Mode with power-shutdown

        1163
    • 5.6. Standby Mode : Stop Mode

      1164
      • 5.6.1. Configuration of Stop Mode

        1165
      • 5.6.2. Activation of Stop Mode

        1166
      • 5.6.3. Wake Up from the Stop Mode

        1167
      • 5.6.4. Effect of Stop Mode

        1168
    • 5.7. Standby Mode : Stop Mode with power-shutdown

      1169
      • 5.7.1. Configuration of Stop Mode with power-shutdown

        1170
      • 5.7.2. Activation of Stop Mode with power-shutdown

        1171
      • 5.7.3. Wake Up from the Stop Mode with power-shutdown

        1173
      • 5.7.4. Effect of Stop Mode with power-shutdown

        1175
    • 5.8. Stop State of Microcontroller

      1176
    • 5.9. Transition to Illegal Standby Mode

      1177
    • 5.10. Restrictions on Power-Shutdown and Normal Standby Control

      1178
  • 6. Example of Use

    1180
• CHAPTER 31: INTERNAL LOW-VOLTAGE DETECTION (INTERNAL POWER SUPPLY LOW-VOLTAGE DETECTION)

  1181
  • 1. Overview

    1182
  • 2. Features

    1183
  • 3. Configuration

    1184
  • 4. Registers

    1185
    • 4.1. Internal Low-Voltage Detection Register : LVD (Low-Voltage Detect internal power fall register)

      1186
  • 5. Operation

    1188
    • 5.1. Internal Low-voltage Detection

      1189
  • 6. Notes

    1190
• CHAPTER 32: LOW-VOLTAGE DETECTION (EXTERNAL LOW-VOLTAGE DETECTION)

  1191
  • 1. Overview

    1192
  • 2. Features

    1193
  • 3. Configuration

    1194
  • 4. Registers

    1195
    • 4.1. External Low-Voltage Detection Rise Detection Register : LVD5R (Low-Voltage Detect external 5v Rise register)

      1196
    • 4.2. External Low-Voltage Detection Fall Detection Register : LVD5F (Low-Voltage Detect external 5v Fall register)

      1197
  • 5. Operation

    1199
  • 6. Notes

    1200
• CHAPTER 33: WILD REGISTER

  1201
  • 1. Overview

    1202
  • 2. Features

    1203
  • 3. Configuration

    1204
  • 4. Registers

    1205
    • 4.1. Wild Register Data Enable Register : WREN (Wild Register ENable register)

      1207
    • 4.2. Wild Register Address Register 00 to 15 : WRAR00 to 15 (Wild Register Address Register 00 to 15)

      1208
    • 4.3. Wild Register Data Register 00 to 15 : WRDR00 to 15 (Wild Register Data Register 00 to 15)

      1209
  • 5. Operation

    1210
  • 6. Usage Example

    1211
• CHAPTER 34: CLOCK SUPERVISOR

  1213
  • 1. Overview

    1214
  • 2. Configuration

    1215
  • 3. Register

    1216
    • 3.1. Clock Supervisor Control Register : CSVCR(Clock SuperVisor Control Register)

      1217
  • 4. Operation

    1220
    • 4.1. Initial State

      1221
    • 4.2. Stopping CR Oscillator and the Clock Supervisor Function

      1222
    • 4.3. Re-enabling the Clock Supervisor

      1223
    • 4.4. Sub Clock Mode

      1224
    • 4.5. Stop Mode

      1225
    • 4.6. Watch Mode

      1226
    • 4.7. Checking the Reset Factor Using the Clock Supervisor

      1227
    • 4.8. Return from CR Clock

      1228
    • 4.9. Sub Clock Mode Enabled by Setting SCKS Bit

      1229
• CHAPTER 35: REGULATOR CONTROL

  1231
  • 1. Overview

    1232
  • 2. Features

    1233
  • 3. Configuration

    1234
  • 4. Register

    1235
    • 4.1. Regulator Output Voltage Select Register : REGSEL (REGulator output voltage SELect register)

      1236
  • 5. Operation

    1238
• CHAPTER 36: EXTERNAL BUS INTERFACE

  1239
  • 1. Overview

    1240
  • 2. Features

    1241
  • 3. Configuration

    1242
  • 4. Registers

    1243
    • 4.1. CS Area Setting Registers: ASR0 to ASR3 (Area Setting Register 0-3)

      1244
    • 4.2. CS Bus Setting Registers: ACR0 to ACR3 (Area Configuration Register 0-3)

      1247
    • 4.3. CS Wait Registers : AWR0 to AWR3 (Area Wait Register 0-3)

      1249
    • 4.4. External DMA Transfer Registers: DMAR0-3 (DMA transfer Register 0-3)

      1254
  • 5. Operation

    1256
    • 5.1. External Pin Table

      1257
    • 5.2. External Bus Signal Protocol

      1259
      • 5.2.1. Address/Data Split Bus Read Protocol

        1259
      • 5.2.2. Address/Data split bus write protocol

        1261
      • 5.2.3. Address/Data multiplexed bus read protocol

        1262
      • 5.2.4. Address/Data multiplexed bus write protocol

        1264
    • 5.3. Address Alignment

      1266
    • 5.4. Split Access

      1267
    • 5.5. Data Alignment

      1268
    • 5.6. Address Information

      1271
      • 5.6.1. Address information and output pins

        1271
      • 5.6.2. Address type

        1271
    • 5.7. Idle Cycle Insertion Function

      1272
    • 5.8. External Bus Output Signal Timing Settings

      1273
    • 5.9. RDY Pin Access Cycle Extension Function

      1278
    • 5.10. CS Setting Flow

      1279
    • 5.11. Example of Connecting to Asynchronous Memory

      1287
    • 5.12. Example of Connection to Little Endian Device

      1288
• CHAPTER 37: BUS PERFORMANCE COUNTERS

  1289
  • 1. Overview

    1290
  • 2. Features

    1291
  • 3. Configuration

    1292
  • 4. Registers

    1293
    • 4.1. BPC-A Control Register : BPCCRA (Bus Performance Counter Control Register A)

      1294
    • 4.2. BPC-B Control Register : BPCCRB (Bus Performance Counter Control Register B)

      1296
    • 4.3. BPC-C Control Register : BPCCRC (Bus Performance Counter Control Register C)

      1297
    • 4.4. BPC-A Count Register : BPCTRA (Bus Performance CounTer Register A)

      1298
    • 4.5. BPC-B Count Register : BPCTRB (Bus Performance CounTer Register B)

      1299
    • 4.6. BPC-C Count Register : BPCTRC (Bus Performance CounTer Register C)

      1300
  • 5. Operation

    1301
    • 5.1. Setting

      1302
    • 5.2. Starting and Stopping

      1304
    • 5.3. Operation

      1305
    • 5.4. Measurement and Result Processing

      1306
• CHAPTER 38: CRC

  1309
  • 1. Overview

    1310
  • 2. Features

    1311
  • 3. Configuration

    1312
  • 4. Registers

    1313
    • 4.1. CRC Control Register : CRCCR (CRC Control Register)

      1314
    • 4.2. CRC Initial Value Register : CRCINIT (CRC Initial value register)

      1315
    • 4.3. CRC Input Data Register : CRCIN (CRC INput data register)

      1316
    • 4.4. CRC Register : CRCR (CRC Register)

      1317
  • 5. Operation

    1318
    • 5.1. CRC Definition

      1319
    • 5.2. Reset Operation

      1320
    • 5.3. Initialization

      1321
    • 5.4. Byte and Bit Orders

      1322
    • 5.5. CRC Calculation Sequence

      1323
    • 5.6. Examples

      1324
      • 5.6.1. Example 1 CRC16, Fixed Byte Input

        1325
      • 5.6.2. Example 2 CRC16, Mixture of Different Input Bit Widths

        1327
      • 5.6.3. Example 3 CRC32, Byte Order, Big-endian

        1328
      • 5.6.4. Example 4 CRC32, Byte Order, Little-endian

        1329
• CHAPTER 39: RAMECC

  1331
  • 1. Overview

    1332
  • 2. Features

    1333
  • 3. Configuration

    1334
  • 4. Registers

    1335
    • 4.1. Single-bit ECC Error Address Register XBS RAM : SEEARX

      1336
    • 4.2. Double-bit ECC Error Address Register XBS RAM : DEEARX

      1337
    • 4.3. ECC Error Control Register XBS RAM : EECSRX

      1338
    • 4.4. ECC False Error Generation Address Register XBS RAM : EFEARX

      1339
    • 4.5. ECC False Error Generation Control Register XBS RAM : EFECRX

      1340
    • 4.6. Single-bit ECC Error Address Register BACKUP-RAM : SEEARA

      1342
    • 4.7. Double-bit ECC Error Address Register BACKUP-RAM : DEEARA

      1343
    • 4.8. ECC Error Control Register BACKUP-RAM : EECSRA

      1344
    • 4.9. ECC False Error Generation Address Register BACKUP-RAM : EFEARA

      1345
    • 4.10. ECC False Error Generation Control Register BACKUP-RAM : EFECRA

      1346
  • 5. Operation

    1348
    • 5.1. RAMECC Function

      1349
    • 5.2. Interrupt-related Register

      1350
    • 5.3. Test Mode

      1351
    • 5.4. Note

      1352
• CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

  1353
  • 1. Overview

    1354
  • 2. Features

    1355
  • 3. Configuration

    1362
  • 4. Registers

    1366
    • 4.1. Common Registers

      1369
      • 4.1.1. Serial Mode Register: SMR

        1370
      • 4.1.2. FIFO Control Register 1: FCR1

        1373
      • 4.1.3. FIFO Control Register 0: FCR0

        1375
      • 4.1.4. FIFO BYTE Register: FBYTE

        1378
      • 4.1.5. Transmission FIFO Interrupt Control Register: FTICR

        1380
    • 4.2. Registers for UART

      1381
      • 4.2.1. Serial Control Register: SCR

        1382
      • 4.2.2. Serial Status Register: SSR

        1384
      • 4.2.3. Extended Serial Control Register: ESCR

        1387
      • 4.2.4. Receive Data Register/Transmit Data Register: RDR/TDR

        1389
      • 4.2.5. Serial Aid Control Status Register: SACSR

        1391
      • 4.2.6. Serial Timer Register: STMR

        1394
      • 4.2.7. Serial timer Comparison Register: STMCR

        1395
      • 4.2.8. Transfer Byte Register: TBYTE

        1396
      • 4.2.9. Baud rate Generator Register: BGR

        1397
    • 4.3. Registers for CSIO

      1398
      • 4.3.1. Serial Control Register: SCR

        1399
      • 4.3.2. Serial Status Register: SSR

        1401
      • 4.3.3. Extended Serial Control Register: ESCR

        1403
      • 4.3.4. Receive Data Register/Transmit Data Register: RDR/TDR

        1405
      • 4.3.5. Serial Aid Control Status Register: SACSR

        1409
      • 4.3.6. Serial Timer Register: STMR

        1413
      • 4.3.7. Serial Timer Compare Register: STMCR

        1414
      • 4.3.8. Serial Chip Select Control Status Register: SCSCR

        1415
      • 4.3.9. Serial Chip Select Timing Register: SCSTR3-0

        1418
      • 4.3.10. Serial Chip Select Format Register: SCSFR2-0

        1421
      • 4.3.11. Transfer Byte Register: TBYTE3-0

        1429
      • 4.3.12. Baud rate Generator Register: BGR

        1431
    • 4.4. Registers for LIN-UART

      1432
      • 4.4.1. Serial Control Register: SCR

        1433
      • 4.4.2. Serial Status Register: SSR

        1435
      • 4.4.3. Extended Serial Control Register: ESCR

        1437
      • 4.4.4. Receive Data Register/Transmit Data Register: RDR/TDR

        1439
      • 4.4.5. Serial Aid Control Status Register: SACSR

        1441
      • 4.4.6. Serial Timer Register: STMR

        1446
      • 4.4.7. Serial Timer Compare Register: STMCR

        1447
      • 4.4.8. Sync Field Upper Limit Register: SFUR

        1448
      • 4.4.9. Sync Field Lower Limit Register: SFLR

        1449
      • 4.4.10. Baud Rate Generator Register: BGR

        1450
      • 4.4.11. LIN Assist Mode Status Register: LAMSR

        1451
      • 4.4.12. LIN Assist Mode Control Register: LAMCR

        1454
      • 4.4.13. LIN Assist Mode Interrupt Enable Register: LAMIER

        1457
      • 4.4.14. LIN Assist Mode Transmission/Reception ID Register: LAMTID / LAMRID

        1459
      • 4.4.15. LIN Assist Mode Error Status Register: LAMESR

        1460
      • 4.4.16. LIN Assist Mode Trouble Examination Register: LAMERT

        1462
    • 4.5. Registers for I2C

      1466
      • 4.5.1. I2C Bus Control Register: IBCR

        1467
      • 4.5.2. Serial Status Register: SSR

        1472
      • 4.5.3. I2C Bus Status Register: IBSR

        1475
      • 4.5.4. Receive Data Register/Transmit Data Register: RDR/TDR

        1479
      • 4.5.5. Serial Aid Control Status Register: SACSR

        1481
      • 4.5.6. Serial Timer Register: STMR

        1484
      • 4.5.7. Serial Timer Compare Register: STMCR

        1485
      • 4.5.8. 7-bit Slave Address Mask Register: ISMK

        1486
      • 4.5.9. 7-bit Slave Address Register: ISBA

        1487
      • 4.5.10. Baud rate Generator Register: BGR

        1488
  • 5. Operation of UART

    1489
    • 5.1. Interrupt of UART

      1490
      • 5.1.1. List of Interrupt of UART

        1491
      • 5.1.2. Reception Interrupts and Flag Setting Timing

        1492
      • 5.1.3. Interrupts when Using Reception FIFO and Flag Setting Timing

        1494
      • 5.1.4. Transmission Interrupts and Flag Setting Timing

        1496
      • 5.1.5. Interrupts When Using Transmission FIFO and Flag Setting Timing

        1497
      • 5.1.6. Timing of Timer Interrupt Generation and Flag Setting

        1498
    • 5.2. Operation of UART

      1499
      • 5.2.1. Transmission/Reception Data Format

        1500
      • 5.2.2. Transmission Operation

        1502
      • 5.2.3. Reception Operation

        1503
      • 5.2.4. Clock Selection

        1504
      • 5.2.5. Start Bit Detection

        1505
      • 5.2.6. Stop Bit

        1506
      • 5.2.7. Error Detection

        1507
      • 5.2.8. Parity Bit

        1508
      • 5.2.9. Data Signaling Method

        1509
      • 5.2.10. Hardware Flow Control

        1510
      • 5.2.11. Operation of Serial Timer

        1512
      • 5.2.12. Test Mode

        1517
      • 5.2.13. UART Baud Rate Selection/Setting

        1518
    • 5.3. Setup Procedure and Program Flow

      1523
      • 5.3.1. Operation Mode 0 (One-to-One Connection)

        1524
      • 5.3.2. Operation Mode 1 (One-to-N Connection)

        1526
  • 6. Operation of CSIO

    1530
    • 6.1. Interrupts of CSIO

      1531
      • 6.1.1. List of Interrupts of CSIO

        1532
      • 6.1.2. Reception Interrupts and Flag Setting Timing

        1533
      • 6.1.3. Interrupts when Using Reception FIFO and Flag Setting Timing

        1534
      • 6.1.4. Transmission Interrupts and Flag Setting Timing

        1536
      • 6.1.5. Interrupts When Using Transmission FIFO and Flag Setting Timing

        1537
      • 6.1.6. Timing of Timer Interrupt and Flag Setting

        1538
      • 6.1.7. Timing of Chip Select Error Generation and Flag Setting

        1539
    • 6.2. Operation of CSIO

      1541
      • 6.2.1. Normal Transfer (I)

        1542
      • 6.2.2. Normal Transfer (II)

        1550
      • 6.2.3. SPI Transfer (I)

        1558
      • 6.2.4. SPI Transfer (II)

        1566
      • 6.2.5. Operation of Serial Timer

        1574
      • 6.2.6. Operation of Serial Chip Select

        1580
      • 6.2.7. Test Mode

        1588
      • 6.2.8. Baud Rate Generation

        1589
    • 6.3. Setup Procedure and Program Flow

      1592
  • 7. Operation of LIN Interface (v2.1)

    1594
    • 7.1. Interrupt of LIN Interface (v2.1) manual mode

      1595
      • 7.1.1. List of Interrupts of LIN-UART Interface (v2.1) (manual mode)

        1596
      • 7.1.2. Reception Interrupts and Flag Setting Timing

        1597
      • 7.1.3. Interrupts when Using Reception FIFO and Flag Setting Timing

        1599
      • 7.1.4. Transmission Interrupts and Flag Setting Timing

        1601
      • 7.1.5. Interrupts When Using Transmission FIFO and Flag Setting Timing

        1602
      • 7.1.6. Timer Interrupt and Flag Setting Timing

        1603
      • 7.1.7. Sync Field Detection Interrupts and Flag Setting Timing

        1604
    • 7.2. Interrupts in LIN Interface (v2.1) Assist Mode

      1605
      • 7.2.1. List of Interrupts of LIN-UART Interface (v2.1) (assist mode)

        1606
      • 7.2.2. Reception Interrupts and Flag Setting Timing in Assist Mode

        1608
      • 7.2.3. Reception Interrupts and Flag Setting Timing under using Reception FIFO

        1614
      • 7.2.4. Transmission Interrupts and Flag Setting Timing

        1615
      • 7.2.5. Interrupts and Flag Setting Timing under using Transmission FIFO

        1616
      • 7.2.6. Timer Interrupts and Flag Setting Timing

        1617
      • 7.2.7. Status Interrupts and Flag Setting Timing in Assist Mode

        1618
    • 7.3. Operation of Serial Timer

      1620
    • 7.4. Test Mode

      1623
      • 7.4.1. Manual Mode

        1624
      • 7.4.2. Assist Mode

        1625
    • 7.5. Operation of LIN Interface (v2.1)

      1630
      • 7.5.1. Manual mode

        1631
      • 7.5.2. Assist Mode

        1644
      • 7.5.3. LIN-UART Baud Rate Selection/Setting

        1662
    • 7.6. Setup Procedure and Program Flow

      1663
      • 7.6.1. Manual mode

        1664
      • 7.6.2. Assist mode

        1668
  • 8. Operation of I2C

    1673
    • 8.1. Interrupts of I2C

      1674
      • 8.1.1. List of Interrupts of I2C Interface

        1674
      • 8.1.2. Timing of Timer Interrupt Generation and Flag Setting

        1676
    • 8.2. Operation for I2C Interface Communication

      1677
      • 8.2.1. I2C Bus Start Condition

        1677
      • 8.2.2. I2C Bus Stop Condition

        1677
      • 8.2.3. I2C Bus Repeated Start Condition

        1677
      • 8.2.4. I2C Bus Error

        1678
      • 8.2.5. Serial Timer Operations

        1679
      • 8.2.6. Baud Rate Generation

        1681
    • 8.3. I2C Master Mode

      1683
      • 8.3.1. Start Condition Generation

        1683
      • 8.3.2. Slave Address Output

        1685
      • 8.3.3. Acknowledge Reception by Transmitting First Byte

        1687
      • 8.3.4. Data Transmission by Master

        1694
      • 8.3.5. Data Reception by Master

        1707
      • 8.3.6. Arbitration Lost

        1713
      • 8.3.7. Wait of the Master Mode

        1713
      • 8.3.8. Repetition Start Condition Issue when DMA Mode Enabled (SSR:DMA=1)

        1714
    • 8.4. I2C Slave Mode

      1715
      • 8.4.1. Detection of Slave Address Matching

        1716
      • 8.4.2. Data Direction Bit

        1717
      • 8.4.3. Slave Mode Reception

        1717
      • 8.4.4. Slave Mode Transmission

        1724
    • 8.5. Example of I2C Flowchart

      1725
• CHAPTER 41: CAN

  1733
  • 1. Overview

    1734
  • 2. Features

    1735
  • 3. Configuration

    1736
  • 4. Registers

    1737
    • 4.1. Overview

      1738
      • 4.1.1. List of Base-addresses (Base-addr), External Pins and Buffer Size

        1739
      • 4.1.2. List of Overall Control Register

        1740
      • 4.1.3. List of Message Interface Register

        1741
      • 4.1.4. List of Message Handler Register

        1744
    • 4.2. Overall Control Registers

      1746
      • 4.2.1. CAN Control Register : CTRLR

        1747
      • 4.2.2. CAN Status Register : STATR

        1750
      • 4.2.3. CAN Error Counter : ERRCNT

        1753
      • 4.2.4. CAN Bit Timing Register : BTR

        1754
      • 4.2.5. CAN Interrupt Register : INTR

        1755
      • 4.2.6. CAN Test Register : TESTR

        1756
      • 4.2.7. CAN Prescaler Extension Register : BRPER

        1758
    • 4.3. Message Interface Register

      1759
      • 4.3.1. IFx Command Request Register : IFxCREQ

        1760
      • 4.3.2. IFx Command Mask Register (IFxCMSK)

        1762
      • 4.3.3. IFx Mask Registers 1, 2 : IFxMSK1, IFxMSK2

        1766
      • 4.3.4. IFx Arbitration Registers 1, 2 : IFxARB1, IFxARB2

        1767
      • 4.3.5. IFx Message Control Register : IFxMCTR

        1768
      • 4.3.6. IFx Data Registers A1, A2, B1, B2 : IFxDTA1, IFxDTA2, IFxDTB1, IFxDTB2

        1769
    • 4.4. Message Object

      1770
      • 4.4.1. Configuration of Message Object

        1771
      • 4.4.2. Functions of Message Object

        1772
    • 4.5. Message Handler Registers

      1777
      • 4.5.1. CAN Transmission Request Registers : TREQR1 to TREQR4

        1778
      • 4.5.2. CAN Data Update Registers : NEWDT1 to NEWDT4

        1781
      • 4.5.3. CAN Interrupt Pending Registers :INTPND1 to INTPND4

        1784
      • 4.5.4. CAN Message Valid Registers : MSGVAL1 to MSGVAL4

        1787
  • 5. Operation

    1790
    • 5.1. Message Object

      1791
      • 5.1.1. Message Object

        1792
      • 5.1.2. Data Transmission/Reception with Message RAM

        1793
    • 5.2. Message Transmission Operation

      1794
      • 5.2.1. Message Transmission

        1795
      • 5.2.2. Transmission Priority

        1796
      • 5.2.3. Transmission Message Object Setting

        1797
      • 5.2.4. Update of Transmission Message Object

        1798
    • 5.3. Message Reception Operation

      1799
      • 5.3.1. Reception Message Acceptance Filter

        1800
      • 5.3.2. Reception Priority

        1801
      • 5.3.3. Data Frame Reception

        1802
      • 5.3.4. Remote Frame

        1803
      • 5.3.5. Reception Message Object Setting

        1804
      • 5.3.6. Reception Message Processing

        1805
    • 5.4. FIFO Buffer Function

      1806
      • 5.4.1. Configuration of FIFO Buffer

        1807
      • 5.4.2. Message Reception by FIFO Buffer

        1808
      • 5.4.3. Reading from FIFO Buffer

        1809
    • 5.5. Interrupt Function

      1811
    • 5.6. Bit Timing and CAN System Clock (fsys) Generation

      1812
    • 5.7. Test Mode

      1815
      • 5.7.1. Test Mode Setting

        1816
      • 5.7.2. Silent Mode

        1817
      • 5.7.3. Loopback Mode

        1818
      • 5.7.4. Combination of Silent and Loopback Modes

        1819
      • 5.7.5. Basic Mode

        1820
      • 5.7.6. Software Control of the CAN_TX Pin

        1821
    • 5.8. Software Initialization

      1822
    • 5.9. CAN Wake Up Function

      1823
• CHAPTER 42: CAN clock prescaler

  1825
  • 1. Overview

    1826
  • 2. Features

    1827
  • 3. Configuration

    1828
  • 4. Registers

    1829
    • 4.1. CAN Prescaler Register : CANPRE

      1830
• CHAPTER 43: D/A CONVERTER

  1833
  • 1. Overview

    1834
  • 2. Features

    1835
  • 3. Configuration

    1836
  • 4. Registers

    1837
    • 4.1. DA Control Register : DACR

      1838
    • 4.2. DA Data Register : DADR

      1839
  • 5. Operation

    1840
  • 6. Note

    1841
• CHAPTER 44: 12-BIT A/D CONVERTER

  1843
  • 1. Overview

    1844
  • 2. Features

    1845
    • 2.1. Function of A/D Activation Compare

      1846
    • 2.2. Function of A/D Activation Arbitration

      1848
    • 2.3. Functions of 12-bit A/D Converter Control

      1849
  • 3. Configuration

    1850
  • 4. Registers

    1853
    • 4.1. Register of Analog Input Control

      1862
      • 4.1.1. Analog Input Enable Register : ADER

        1863
    • 4.2. Register of A/D Activation Compare

      1865
      • 4.2.1. A/D Software Activation Register: ADTSS0, ADTSS1

        1866
      • 4.2.2. A/D Software Activation Channel Select Register : ADTSE0, ADTSE1

        1867
      • 4.2.3. Compare Buffer Register / Compare Register : ADCOMPB0 to ADCOMPB47 / ADCOMP0 to ADCOMP47

        1869
      • 4.2.4. A/D Activation Trigger Control Status Register : ADTCS0 to ADTCS47

        1871
      • 4.2.5. A/D Data Register : ADTCD0 to ADTCD47

        1876
      • 4.2.6. A/D Activation Trigger Extend Control Register : ADTECS0 to ADTECS47

        1878
      • 4.2.7. Upper Bound Threshold Setting Register : ADRCUT0 to ADRCUT7

        1881
      • 4.2.8. Lower Bound Threshold Setting Register : ADRCLT0 to ADRCLT7

        1882
      • 4.2.9. Range Compare Control Status Register: ADRCCS0 to ADRCCS47

        1883
      • 4.2.10. Range Compare Threshold Over Flag Register : ADRCOT0, ADRCOT1

        1886
      • 4.2.11. Range Compare Flag Register : ADRCIF0, ADRCIF1

        1888
      • 4.2.12. Scan Conversion Control Status Register : ADSCANS0, ADSCANS1

        1891
      • 4.2.13. Activation Channel Conversion Count Setting Register : ADNCS0 to ADNCS23

        1893
      • 4.2.14. Data Protection Status Flag Register : ADPRTF0, ADPRTF1

        1895
      • 4.2.15. Activation Channel Conversion Completion Flag Register : ADEOCF0, ADEOCF1

        1897
    • 4.3. Register of 12-BIT A/D Converter Control

      1899
      • 4.3.1. A/D Control Status Register: ADCS0, ADCS1

        1900
      • 4.3.2. A/D Channel Status Register : ADCH

        1901
      • 4.3.3. A/D Mode Setting Register : ADMD

        1902
      • 4.3.4. A/D Sampling Time Setting Per Channel Register : ADSTPCS

        1905
  • 5. Operation

    1907
    • 5.1. Interrupt of A/D activation compare

      1908
      • 5.1.1. A/D conversion completion interrupt

        1909
      • 5.1.2. Scan conversion completion interrupt by conversion count specification

        1910
      • 5.1.3. Range comparison interrupt

        1911
    • 5.2. A/D activation compare operation

      1912
      • 5.2.1. A/D activation

        1913
      • 5.2.2. A/D activation enable

        1914
      • 5.2.3. Free-run timer input

        1915
      • 5.2.4. Analog channel select

        1916
      • 5.2.5. Software activation

        1917
      • 5.2.6. External trigger activation

        1918
      • 5.2.7. Reload timer activation

        1919
      • 5.2.8. Compare match activation

        1920
      • 5.2.9. PPG activation

        1926
      • 5.2.10. Activation request mode

        1927
      • 5.2.11. A/D conversion data

        1928
      • 5.2.12. Protection function

        1929
      • 5.2.13. Scan conversion mode

        1930
      • 5.2.14. High priority activation request operation of other activation channel during the scan conversion

        1936
      • 5.2.15. Forced termination of activation request

        1938
      • 5.2.16. Range comparison function

        1939
    • 5.3. A/D Activation Arbitration Operation

      1944
      • 5.3.1. A/D Activation Trigger Arbitration

        1945
      • 5.3.2. Analog Channel Select

        1946
      • 5.3.3. A/D Conversion Cancel Function

        1947
    • 5.4. 12-bit A/D Converter Operation

      1948
      • 5.4.1. Operation Timing

        1949
      • 5.4.2. Activation Factors

        1950
      • 5.4.3. A/D Conversion

        1951
      • 5.4.4. Re-activation

        1952
      • 5.4.5. A/D Conversion Cancel

        1953
      • 5.4.6. Analog Channel Select Control

        1954
      • 5.4.7. A/D Conversion Time

        1955
      • 5.4.8. A/D Conversion Completion and A/D Data Retrieval

        1956
      • 5.4.9. Power down

        1957
  • 6. Notes

    1958
• CHAPTER 45: FLASH MEMORY

  1961
  • 1. Overview

    1962
  • 2. Features

    1963
  • 3. Configuration

    1964
    • 3.1. Block Diagram

      1965
    • 3.2. Sector Configuration Diagram

      1966
    • 3.3. Sector Number and Flash Macro Number Correspondence Chart

      1969
  • 4. Registers

    1975
    • 4.1. Flash Control Register : FCTLR (Flash ConTroL Register)

      1976
    • 4.2. Flash Status Register : FSTR (Flash STatus Register)

      1978
    • 4.3. Flash Interface Control Register : FLIFCTLR(Flash I/F Control Register)

      1980
    • 4.4. Flash I/F Feature Extension Register 1: FLIFFER1

      1981
    • 4.5. Flash I/F Feature Extension Register 2: FLIFFER2

      1982
  • 5. Operation

    1983
    • 5.1. Access Mode Setting

      1984
      • 5.1.1. Configuring CPU-ROM Mode

        1985
      • 5.1.2. Configuring CPU Programming Mode

        1986
    • 5.2. Programming Flash Memory by CPU

      1987
    • 5.3. Automatic Algorithm

      1988
      • 5.3.1. Command Sequence

        1989
      • 5.3.2. Automatic Algorithm Execution State

        1992
    • 5.4. Reset Command

      1996
    • 5.5. Write Command

      1997
    • 5.6. Chip Erase Command

      2000
    • 5.7. Sector Erase Command

      2001
    • 5.8. Sector Erase Suspend Command

      2004
    • 5.9. Security Function

      2005
      • 5.9.1. Flash Security On/Off Determination When Reset Released

        2006
      • 5.9.2. Flash Security Setting Method

        2007
      • 5.9.3. Unlocking Flash Security

        2008
      • 5.9.4. Flash Access Restrictions When Security is ON

        2009
    • 5.10. Notes on Using Flash Memory

      2010
• CHAPTER 46: WORKFLASH MEMORY

  2011
  • 1. Overview

    2012
  • 2. Features

    2013
  • 3. Configuration

    2014
    • 3.1. Block Diagram

      2015
    • 3.2. Sector Configuration Diagram

      2016
  • 4. Registers

    2017
    • 4.1. WorkFlash Control Register : DFCTLR (WorkFlash ConTroL Register)

      2018
    • 4.2. WorkFlash Status Register : DFSTR (WorkFlash STatus Register)

      2019
    • 4.3. Flash Interface Control Register : FLIFCTLR (Flash I/F Control Register)

      2021
  • 5. Operation

    2022
    • 5.1. Access Mode Setting

      2023
      • 5.1.1. Configuring CPU-ROM Mode below

        2024
      • 5.1.2. Configuring CPU Programming Mode

        2025
    • 5.2. Writing Flash Memory by CPU

      2026
    • 5.3. Automatic Algorithm

      2027
      • 5.3.1. Command Sequence

        2028
      • 5.3.2. Automatic Algorithm Execution State

        2032
    • 5.4. Reset Command

      2036
    • 5.5. Write Command

      2037
    • 5.6. Chip Erase Command

      2040
    • 5.7. Sector Erase Command

      2041
    • 5.8. Sector Erase Suspend Command

      2043
    • 5.9. Security Function

      2044
      • 5.9.1. Flash Security On/Off Determination When Reset Released

        2045
      • 5.9.2. Flash Security Setting Method

        2046
      • 5.9.3. Unlocking Flash Security

        2047
      • 5.9.4. Flash Access Restrictions When Security is ON

        2048
    • 5.10. Notes on Using Flash Memory

      2049
• CHAPTER 47: ON CHIP DEBUGGER : OCD

  2051
  • 1. Overview

    2052
  • 2. Features

    2053
  • 3. Configuration

    2054
    • 3.1. DEBUG I/F Clock

      2056
      • 3.1.1. DEBUG I/F Main Clock : M_MCLK

        2057
      • 3.1.2. DEBUG I/F PLL Clock : M_PCLK

        2058
  • 4. Registers

    2059
    • 4.1. DBG Register

      2060
      • 4.1.1. DSU Control Register : DSUCR

        2061
    • 4.2. User IO Register

      2062
      • 4.2.1. User Event Register : UER

        2063
      • 4.2.2. High-Speed Communication Frequency Register : HSCFR

        2064
      • 4.2.3. Message Buffer : MBR

        2065
  • 5. Operation

    2066
    • 5.1. OCDU Operating Mode

      2067
      • 5.1.1. Operating Mode

        2068
      • 5.1.2. Operating Mode Status Transition

        2069
    • 5.2. Overview of DEBUG I/F

      2070
      • 5.2.1. Chip Reset Sequence

        2071
      • 5.2.2. Security Function

        2073
    • 5.3. Specification Restrictions at Connection to OCD Tool of This Series

      2074
      • 5.3.1. Clock Setting

        2075
      • 5.3.2. Standby Mode

        2076
      • 5.3.3. Clock Reset State Transitions

        2077
      • 5.3.4. Summary of Specification Restrictions

        2079
    • 5.4. OCD-DSU ID Code and Mount Type Information on This Series

      2084
• CHAPTER 48: WAVEFORM GENERATOR

  2085
  • 1. Overview

    2086
  • 2. Features

    2087
  • 3. Configuration

    2088
  • 4. Registers

    2090
    • 4.1. Registers for the Waveform Generator

      2091
      • 4.1.1. 16-bit Dead Timer Register (TMRR)

        2092
      • 4.1.2. 16-bit Dead Timer State Control Register (DTSCR)

        2093
      • 4.1.3. 16-bit Dead Timer Reload Interrupt Register (DTIR)

        2102
      • 4.1.4. 16-bit Dead Timer Minus Control Register (DTMNS)

        2104
      • 4.1.5. Waveform Control Register 1/2 (SIGCR1, SIGCR2)

        2106
      • 4.1.6. PPG Output Control Register (PICS)

        2109
  • 5. Operation

    2111
    • 5.1. Interrupts for Waveform Generator

      2112
    • 5.2. Operation of the Waveform Generator

      2113
  • 6. Notes

    2131
• CHAPTER 49: BUS DIAGNOSIS FUNCTION

  2133
  • 1. Overview

    2134
  • 2. Features

    2135
  • 3. Configuration

    2136
  • 4. Registers

    2139
    • 4.1. Bus Diagnosis Status Register : BUSDIGSR

      2140
    • 4.2. Bus Diagnosis Test Register : BUSTSTR0/1

      2143
    • 4.3. Bus Diagnosis Address Register : BUSADR

      2148
  • 5. Operation

    2150
    • 5.1. Error detection

      2151
    • 5.2. Test function

      2153
    • 5.3. Notes

      2154
    • 5.4. Example of operating bus diagnosis

      2155
• CHAPTER 50: RAM DIAGNOSIS FUNCTION

  2161
  • 1. Overview

    2162
  • 2. Features

    2163
  • 3. Configuration

    2164
  • 4. Registers

    2165
    • 4.1. TEST Error Address Register 0 XBS RAM : TEAR0X

      2166
    • 4.2. TEST Error Address Register 1 XBS RAM : TEAR1X

      2168
    • 4.3. TEST Error Address Register 2 XBS RAM : TEAR2X

      2170
    • 4.4. TEST Start Address Register XBS RAM : TASARX

      2172
    • 4.5. TEST End Address Register XBS RAM : TAEARX

      2173
    • 4.6. TEST Diagnosis Function Register XBS RAM : TTCRX

      2174
    • 4.7. TEST Initialization Function Register XBS RAM : TICRX

      2177
    • 4.8. TEST Soft Reset Generation Control Register XBS RAM : TSRCRX

      2179
    • 4.9. TEST Fake Error Generation Control Register XBS RAM : TFECRX

      2180
    • 4.10. TEST Key Code Control Register XBS RAM : TKCCRX

      2181
    • 4.11. TEST Error Address Register 0 BACKUP-RAM : TEAR0A

      2182
    • 4.12. TEST Error Address Register 1 BACKUP-RAM : TEAR1A

      2184
    • 4.13. TEST Error Address Register 2 BACKUP-RAM : TEAR2A

      2186
    • 4.14. TEST Start Address Register BACKUP-RAM : TASARA

      2188
    • 4.15. TEST End Address Register BACKUP-RAM : TAEARA

      2189
    • 4.16. TEST Diagnosis Function Register BACKUP-RAM : TTCRA

      2190
    • 4.17. TEST Initialization Function Register BACKUP-RAM : TICRA

      2193
    • 4.18. TEST Soft Reset Generation Control Register BACKUP-RAM : TSRCRA

      2195
    • 4.19. TEST Fake Error Generation Control Register BACKUP-RAM : TFECRA

      2196
    • 4.20. TEST Key Code Control Register BACKUP-RAM : TKCCRA

      2197
  • 5. Operation

    2198
    • 5.1. RAM Diagnosis

      2199
    • 5.2. RAM Initialization

      2200
    • 5.3. Interrupt-Related Register

      2201
    • 5.4. RAM Diagnosis Fake Error Generation Procedure

      2202
    • 5.5. Number of Required Cycles

      2203
    • 5.6. Note

      2205
• CHAPTER 51: TIMING PROTECTION UNIT

  2207
  • 1. Overview

    2208
  • 2. Features

    2209
  • 3. Configuration

    2210
  • 4. Registers

    2211
    • 4.1. TPU Unlock Register : TPUUNLOCK

      2212
    • 4.2. TPU Lock Status Register : TPULST

      2213
    • 4.3. TPU Access Violation Status Register : TPUVST

      2214
    • 4.4. TPU Configuration Register : TPUCFG

      2215
    • 4.5. TPU Timer Interrupt Request Register : TPUTIR

      2217
    • 4.6. TPU Timer Status Register : TPUTST

      2218
    • 4.7. TPU Timer Interrupt Enable Register : TPUTIE

      2219
    • 4.8. TPU Module ID Register : TPUTMID

      2220
    • 4.9. TPU Timer Control Register 00 to 07 : TPUTCN00 to 07

      2221
    • 4.10. TPU Timer Control Register 10 to 17 : TPUTCN10 to 17

      2223
    • 4.11. TPU Timer Current Count Register 0 to 7 : TPUTCC0 to 7

      2225
  • 5. Operation

    2226
    • 5.1. TPU Control Register Access Protection

      2227
    • 5.2. Global Prescaler

      2228
    • 5.3. Interrupt Control

      2229
    • 5.4. Timer Operation

      2230
    • 5.5. Free-run Function

      2231
    • 5.6. Individual Prescaler Function

      2232
    • 5.7. Debug Support Function

      2233
    • 5.8. Operation Flow

      2234
• CHAPTER 52: CLOCK MONITOR

  2235
  • 1. Overview

    2236
  • 2. Features

    2237
  • 3. Configuration

    2238
  • 4. Registers

    2239
    • 4.1. Clock Monitor Configuration Registers : CMCFG

      2239
  • 5. Operation Description

    2241
  • 6. Setup

    2242
  • 7. Q&A

    2243
    • 7.1. How Do I Configure the Output Pin (MONCLK)?

      2244
    • 7.2. How Do I Select the Output Frequency?

      2245
    • 7.3. How Do I Enable or Disable Clock Monitor Output?

      2246
    • 7.4. How Do I Set the Clock Output Mark Level?

      2247
  • 8. Notes

    2248
• APPENDIX

  2249
  • A. I/O Map

    2250
  • B. List of Interrupt Vector

    2310
  • C. Pins Statuses in State of CPU

    2334