Справочник ПользователяСодержаниеChapter 1: LPC24XX Introductory information31. Introduction32. How to read this manual33. LPC2400 features44. Applications65. Ordering options65.1 LPC2458 ordering options65.2 LPC2460 ordering options65.3 LPC2468 ordering options75.4 LPC2470 ordering options75.5 LPC2478 ordering options86. Architectural overview87. On-chip flash programming memory (LPC2458/68/78)98. On-chip SRAM109. LPC2458 block diagram1110. LPC2420/60 block diagram1211. LPC2468 block diagram1312. LPC2470 block diagram1413. LPC2478 block diagram15Chapter 2: LPC24XX Memory mapping161. How to read this chapter162. Memory map and peripheral addressing163. Memory maps184. APB peripheral addresses225. LPC2400 memory re-mapping and boot ROM235.1 Memory map concepts and operating modes235.2 Memory re-mapping246. Memory mapping control256.1 Memory Mapping Control Register (MEMMAP - 0xE01F C040)256.2 Memory mapping control usage notes257. Prefetch abort and data abort exceptions27Chapter 3: LPC24XX System control281. Summary of system control block functions282. Pin description283. Register description283.1 External interrupt inputs293.2 Reset323.3 Other system controls and status flags353.4 AHB Configuration364. Brown-out detection405. Code security vs. debugging40Chapter 4: LPC24XX Clocking and power control411. Summary of clocking and power control functions412. Oscillators432.1 Internal RC oscillator432.2 Main oscillator432.3 RTC oscillator453. Register description453.1 Clock source selection multiplexer453.2 PLL (Phase Locked Loop)463.3 Clock dividers563.4 Power control594. Power domains655. Wakeup timer65Chapter 5: LPC24XX External Memory Controller (EMC)671. How to read this chapter672. Basic configuration673. Introduction684. Features685. EMC functional description685.1 AHB slave register interface695.2 AHB slave memory interface705.3 Pad interface705.4 Data buffers705.5 Memory controller state machine716. Low-power operation716.1 Low-power SDRAM Deep-sleep Mode726.2 Low-power SDRAM partial array refresh727. Memory bank select728. Reset739. Pin description7310. Register description7410.1 EMC Control register (EMCControl - 0xFFE0 8000)7610.2 EMC Status register (EMCStatus - 0xFFE0 8004)7710.3 EMC Configuration register (EMCConfig - 0xFFE0 8008)7810.4 Dynamic Memory Control register (EMCDynamicControl - 0xFFE0 8020)7810.5 Dynamic Memory Refresh Timer register (EMCDynamicRefresh - 0xFFE0 8024)8010.6 Dynamic Memory Read Configuration register (EMCDynamicReadConfig - 0xFFE0 8028)8110.7 Dynamic Memory Percentage Command Period register (EMCDynamictRP - 0xFFE0 8030)8110.8 Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS - 0xFFE0 8034)8210.9 Dynamic Memory Self-refresh Exit Time register (EMCDynamictSREX - 0xFFE0 8038)8210.10 Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR - 0xFFE0 803C)8310.11 Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL - 0xFFE0 8040)8310.12 Dynamic Memory Write Recovery Time register (EMCDynamictWR - 0xFFE0 8044)8410.13 Dynamic Memory Active to Active Command Period register (EMCDynamictRC - 0xFFE0 8048)8410.14 Dynamic Memory Auto-refresh Period register (EMCDynamictRFC - 0xFFE0 804C)8510.15 Dynamic Memory Exit Self-refresh register (EMCDynamictXSR - 0xFFE0 8050)8510.16 Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD - 0xFFE0 8054)8610.17 Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD - 0xFFE0 8058)8610.18 Static Memory Extended Wait register (EMCStaticExtendedWait - 0xFFE0 8080)8710.19 Dynamic Memory Configuration registers (EMCDynamicConfig0-3 - 0xFFE0 8100, 120, 140, 160)8710.20 Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3 - 0xFFE0 8104, 124, 144, 164)9010.21 Static Memory Configuration registers (EMCStaticConfig0-3 - 0xFFE0 8200, 220, 240, 260)9110.22 Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3 - 0xFFE0 8204, 224, 244 ,264)9210.23 Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3 - 0xFFE0 8208, 228, 248, 268)9310.24 Static Memory Read Delay registers (EMCStaticWaitRd0-3 - 0xFFE0 820C, 22C, 24C, 26C)9310.25 Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3 - 0xFFE0 8210, 230, 250, 270)9410.26 Static Memory Write Delay registers (EMCStaticWaitwr0-3 - 0xFFE0 8214, 234, 254, 274)9410.27 Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3 - 0xFFE0 8218, 238, 258, 278)9511. External memory interface9511.1 32-bit wide memory bank connection9611.2 16-bit wide memory bank connection9711.3 8-bit wide memory bank connection9811.4 Memory configuration example99Chapter 6: LPC24XX Memory Accelerator Module (MAM)1001. How to read this chapter1002. Introduction1003. Operation1004. Memory Acceleration Module blocks1014.1 Flash memory bank1014.2 Instruction latches and data latches1024.3 Flash programming Issues1025. Memory Accelerator Module operating modes1026. MAM configuration1037. Register description1047.1 MAM Control Register (MAMCR - 0xE01F C000)1047.2 MAM Timing Register (MAMTIM - 0xE01F C004)1048. MAM usage notes106Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)1081. Features1082. Description1083. Register description1083.1 Software Interrupt Register (VICSoftInt - 0xFFFF F018)1113.2 Software Interrupt Clear Register (VICSoftIntClear - 0xFFFF F01C)1113.3 Raw Interrupt Status Register (VICRawIntr - 0xFFFF F008)1113.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010)1123.5 Interrupt Enable Clear Register (VICIntEnClear - 0xFFFF F014)1123.6 Interrupt Select Register (VICIntSelect - 0xFFFF F00C)1123.7 IRQ Status Register (VICIRQStatus - 0xFFFF F000)1133.8 FIQ Status Register (VICFIQStatus - 0xFFFF F004)1133.9 Vector Address Registers 0-31 (VICVectAddr0-31 - 0xFFFF F100 to 17C)1133.10 Vector Priority Registers 0-31 (VICVectPriority0-31 - 0xFFFF F200 to 27C)1143.11 Vector Address Register (VICAddress - 0xFFFF FF00)1143.12 Software Priority Mask Register (VICSWPriorityMask - 0xFFFF F024)1143.13 Protection Enable Register (VICProtection - 0xFFFF F020)1154. Interrupt sources115Chapter 8: LPC24XX Pin configuration1191. How to read this chapter1192. LPC2400 pin packages1192.1 LPC2400 180-pin package1192.2 LPC2400 208-pin packages1203. LPC2458 pinning information1204. LPC2460/68 pinning information1365. LPC2470/78 pinning information1546. LPC2460/70 boot control174Chapter 9: LPC24XX Pin connect1761. How to read this chapter1762. Description1763. Pin function select register values1774. Pin mode select register values1775. Register description1775.1 Pin Function Select register 0 (PINSEL0 - 0xE002 C000)1785.2 Pin Function Select Register 1 (PINSEL1 - 0xE002 C004)1795.3 Pin Function Select register 2 (PINSEL2 - 0xE002 C008)1805.4 Pin Function Select Register 3 (PINSEL3 - 0xE002 C00C)1805.5 Pin Function Select Register 4 (PINSEL4 - 0xE002 C010)1815.6 Pin Function Select Register 5 (PINSEL5 - 0xE002 C014)1835.7 Pin Function Select Register 6 (PINSEL6 - 0xE002 C018)1855.8 Pin Function Select Register 7 (PINSEL7 - 0xE002 C01C)1855.9 Pin Function Select Register 8 (PINSEL8 - 0xE002 C020)1865.10 Pin Function Select Register 9 (PINSEL9 - 0xE002 C024)1875.11 Pin Function Select Register 10 (PINSEL10 - 0xE002 C028)1885.12 Pin Function Select Register 11 (PINSEL11 - 0xE002 C02C)1895.13 Pin Mode select register 0 (PINMODE0 - 0xE002 C040)1895.14 Pin Mode select register 1 (PINMODE1 - 0xE002 C044)1905.15 Pin Mode select register 2 (PINMODE2 - 0xE002 C048)1905.16 Pin Mode select register 3 (PINMODE3 - 0xE002 C04C)1905.17 Pin Mode select register 4 (PINMODE4 - 0xE002 C050)1905.18 Pin Mode select register 5 (PINMODE5 - 0xE002 C054)1915.19 Pin Mode select register 6 (PINMODE6 - 0xE002 C058)1915.20 Pin Mode select register 7 (PINMODE7 - 0xE002 C05C)1915.21 Pin Mode select register 8 (PINMODE8 - 0xE002 C060)1915.22 Pin Mode select register 9 (PINMODE9 - 0xE002 C064)192Chapter 10: LPC24XX General Purpose Input/Output (GPIO)1931. How to read this chapter1932. Basic configuration1933. Features1933.1 Digital I/O ports1933.2 Interrupt generating digital ports1944. Applications1945. Pin description1956. Register description1956.1 GPIO port Direction register IODIR and FIODIR(IO[0/1]DIR - 0xE002 80[0/1]8 and FIO[0/1/2/3/4]DIR - 0x3FFF C0[0/2/4/6/8]0)1986.2 GPIO port output Set register IOSET and FIOSET(IO[0/1]SET - 0xE002 80[0/1]4 and FIO[0/1/2/3/4]SET - 0x3FFF C0[1/3/5/7/9]8)1996.3 GPIO port output Clear register IOCLR and FIOCLR (IO[0/1]CLR - 0xE002 80[0/1]C and FIO[0/1/2/3/4]CLR - 0x3FFF C0[1/3/5/7/9]C)2016.4 GPIO port Pin value register IOPIN and FIOPIN (IO[0/1]PIN - 0xE002 80[0/1]0 and FIO[0/1/2/3/4]PIN - 0x3FFF C0[1/3/5/7/9]4)2026.5 Fast GPIO port Mask register FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0)2046.6 GPIO interrupt registers2067. GPIO usage notes2087.1 Example 1: sequential accesses to IOSET and IOCLR affecting the same GPIO pin/bit2087.2 Example 2: an instantaneous output of 0s and 1s on a GPIO port2087.3 Writing to IOSET/IOCLR vs. IOPIN2097.4 Output signal frequency considerations when using the legacy and enhanced GPIO registers209Chapter 11: LPC24XX Ethernet2101. How to read this chapter2102. Basic configuration2103. Introduction2104. Features2115. Ethernet architecture2125.1 Partitioning2135.2 Example PHY Devices2145.3 DMA engine functions2145.4 Overview of DMA operation2155.5 Ethernet Packet2156. Pin description2167. Register description2177.1 Ethernet MAC register definitions2197.2 Control register definitions2277.3 Receive filter register definitions2357.4 Module control register definitions2378. Descriptor and status formats2408.1 Receive descriptors and statuses2408.2 Transmit descriptors and statuses2449. Ethernet block functional description2469.1 Overview2469.2 AHB interface2479.3 Interrupts2479.4 Direct Memory Access (DMA)2479.5 Initialization2509.6 Transmit process2519.7 Receive process2579.8 Transmission retry2639.9 Status hash CRC calculations2639.10 Duplex modes2649.11 IEE 802.3/Clause 31 flow control2649.12 Half-Duplex mode backpressure2669.13 Receive filtering2679.14 Power management2699.15 Wake-up on LAN2709.16 Enabling and disabling receive and transmit2719.17 Transmission padding and CRC2739.18 Huge frames and frame length checking2749.19 Statistics counters2749.20 MAC status vectors2749.21 Reset2759.22 Ethernet errors2769.23 AHB bandwidth2769.24 CRC calculation278Chapter 12: LPC24XX LCD controller2801. How to read this chapter2802. Basic configuration2803. Introduction2804. Features2804.1 Programmable parameters2814.2 Hardware cursor support2814.3 Types of LCD panels supported2824.4 TFT panels2824.5 Color STN panels2824.6 Monochrome STN panels2835. Pin description2835.1 Signal usage2836. LCD controller functional description2856.1 AHB interfaces2866.2 Dual DMA FIFOs and associated control logic2876.3 Pixel serializer2876.4 RAM palette2916.5 Hardware cursor2936.6 Gray scaler2986.7 Upper and lower panel formatters2986.8 Panel clock generator2996.9 Timing controller2996.10 STN and TFT data select2996.11 Interrupt generation2996.12 LCD power up and power down sequence3017. Register description3027.1 LCD Configuration register (LCD_CFG, RW - 0xE01F C1B8)3037.2 Horizontal Timing register (LCD_TIMH, RW - 0xFFE1 0000)3037.3 Vertical Timing register (LCD_TIMV, RW - 0xFFE1 0004)3057.4 Clock and Signal Polarity register (LCD_POL, RW - 0xFFE1 0008)3067.5 Line End Control register (LCD_LE, RW - 0xFFE1 000C)3087.6 Upper Panel Frame Base Address register (LCD_UPBASE, RW - 0xFFE1 0010)3097.7 Lower Panel Frame Base Address register (LCD_LPBASE, RW - 0xFFE1 0014)3097.8 LCD Control register (LCD_CTRL, RW - 0xFFE1 0018)3107.9 Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)3127.10 Raw Interrupt Status register (LCD_INTRAW, RW - 0xFFE1 0020)3137.11 Masked Interrupt Status register (LCD_INTSTAT, RW - 0xFFE1 0024)3147.12 Interrupt Clear register (LCD_INTCLR, RW - 0xFFE1 0028)3147.13 Upper Panel Current Address register (LCD_UPCURR, RW - 0xFFE1 002C)3157.14 Lower Panel Current Address register (LCD_LPCURR, RW - 0xFFE1 0030)3157.15 Color Palette registers (LCD_PAL, RW - 0xFFE1 0200 to 0xFFE1 03FC)3157.16 Cursor Image registers (CRSR_IMG, RW - 0xFFE1 0800 to 0xFFE1 0BFC)3167.17 Cursor Control register (CRSR_CTRL, RW - 0xFFE1 0C00)3177.18 Cursor Configuration register (CRSR_CFG, RW - 0xFFE1 0C04)3177.19 Cursor Palette register 0 (CRSR_PAL0, RW - 0xFFE1 0C08)3187.20 Cursor Palette register 1 (CRSR_PAL1, RW - 0xFFE1 0C0C)3187.21 Cursor XY Position register (CRSR_XY, RW - 0xFFE1 0C10)3197.22 Cursor Clip Position register (CRSR_CLIP, RW - 0xFFE1 0C14)3197.23 Cursor Interrupt Mask register (CRSR_INTMSK, RW - 0xFFE1 0C20)3207.24 Cursor Interrupt Clear register (CRSR_INTCLR, RW - 0xFFE1 0C24)3207.25 Cursor Raw Interrupt Status register (CRSR_INTRAW, RW - 0xFFE1 0C28)3217.26 Cursor Masked Interrupt Status register (CRSR_INTSTAT, RW - 0xFFE1 0C2C)3218. LCD timing diagrams3229. LCD panel signal usage324Chapter 13: LPC24XX USB device controller3281. Basic configuration3282. Introduction3283. Features3294. Fixed endpoint configuration3295. Functional description3305.1 Analog transceiver3315.2 Serial Interface Engine (SIE)3315.3 Endpoint RAM (EP_RAM)3315.4 EP_RAM access control3315.5 DMA engine and bus master interface3325.6 Register interface3325.7 SoftConnect3325.8 GoodLink3326. Operational overview3327. Pin description3337.1 USB device usage note3338. Clocking and power management3338.1 Power requirements3348.2 Clocks3348.3 Power management support3348.4 Remote wake-up3359. Register description3359.1 Port select register3369.2 Clock control registers3379.3 Device interrupt registers3389.4 Endpoint interrupt registers3429.5 Endpoint realization registers3469.6 USB transfer registers3499.7 SIE command code registers3519.8 DMA registers35210. Interrupt handling35911. Serial interface engine command description36211.1 Set Address (Command: 0xD0, Data: write 1 byte)36311.2 Configure Device (Command: 0xD8, Data: write 1 byte)36311.3 Set Mode (Command: 0xF3, Data: write 1 byte)36411.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes)36511.5 Read Test Register (Command: 0xFD, Data: read 2 bytes)36511.6 Set Device Status (Command: 0xFE, Data: write 1 byte)36511.7 Get Device Status (Command: 0xFE, Data: read 1 byte)36611.8 Get Error Code (Command: 0xFF, Data: read 1 byte)36611.9 Read Error Status (Command: 0xFB, Data: read 1 byte)36711.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))36811.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1 byte)36911.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte (optional))36911.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))37011.14 Validate Buffer (Command: 0xFA, Data: none)37012. USB device controller initialization37113. Slave mode operation37213.1 Interrupt generation37213.2 Data transfer for OUT endpoints37213.3 Data transfer for IN endpoints37314. DMA operation37314.1 Transfer terminology37314.2 USB device communication area37414.3 Triggering the DMA engine37414.4 The DMA descriptor37514.5 Non-isochronous endpoint operation37814.6 Isochronous endpoint operation38014.7 Auto Length Transfer Extraction (ATLE) mode operation38215. Double buffered endpoint operation38515.1 Bulk endpoints38515.2 Isochronous endpoints387Chapter 14: LPC24XX USB Host controller3881. Basic configuration3882. Introduction3882.1 Features3882.2 Architecture3893. Interfaces3893.1 Pin description3893.2 Software interface390Chapter 15: LPC24XX USB OTG controller3931. Basic configuration3932. Introduction3933. Features3934. Architecture3935. Modes of operation3946. Pin configuration3946.1 Connecting port U1 to an external OTG transceiver3956.2 Connecting USB as a two-port host3986.3 Connecting USB as one port host and one port device3987. Register description3997.1 USB Interrupt Status Register (USBIntSt - 0xE01F C1C0)4007.2 OTG Interrupt Status Register (OTGIntSt - 0xE01F C100)4017.3 OTG Interrupt Enable Register (OTGIntEn - 0xFFE0 C104)4017.4 OTG Interrupt Set Register (OTGIntSet - 0xFFE0 C20C)4017.5 OTG Interrupt Clear Register (OTGIntClr - 0xFFE0 C10C)4017.6 OTG Status and Control Register (OTGStCtrl - 0xFFE0 C110)4017.7 OTG Timer Register (OTGTmr - 0xFFE0 C114)4037.8 OTG Clock Control Register (OTGClkCtrl - 0xFFE0 CFF4)4037.9 OTG Clock Status Register (OTGClkSt - 0xFFE0 CFF8)4047.10 I2C Receive Register (I2C_RX - 0xFFE0 C300)4057.11 I2C Transmit Register (I2C_TX - 0xFFE0 C300)4057.12 I2C Status Register (I2C_STS - 0xFFE0 C304)4057.13 I2C Control Register (I2C_CTL - 0xFFE0 C308)4077.14 I2C Clock High Register (I2C_CLKHI - 0xFFE0 C30C)4087.15 I2C Clock Low Register (I2C_CLKLO - 0xFFE0 C310)4097.16 Interrupt handling4098. HNP support4108.1 B-device: peripheral to host switching4118.2 A-device: host to peripheral HNP switching4149. Clocking and power management4189.1 Device clock request signals4199.2 Power-down mode support42010. USB OTG controller initialization420Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter (UART) 0/2/34221. Basic configuration4222. Features4223. Pin description4224. Register description42316.4.1 UARTn Receiver Buffer Register (U0RBR - 0xE000 C000, U2RBR - 0xE007 8000, U3RBR - 0xE007 C000 when DLAB = 0, Read Only)4264.2 UARTn Transmit Holding Register (U0THR - 0xE000 C000, U2THR - 0xE007 8000, U3THR - 0xE007 C000 when DLAB = 0, Write Only)4264.3 UARTn Divisor Latch LSB Register (U0DLL - 0xE000 C000, U2DLL - 0xE007 8000, U3DLL - 0xE007 C000 when DLAB = 1) and UARTn Divisor Latch MSB Register (U0DLM - 0xE000 C004, U2DLL - 0xE007 8004, U3DLL - 0xE007 C004 when DLAB = 1)4264.4 UARTn Interrupt Enable Register (U0IER - 0xE000 C004, U2IER - 0xE007 8004, U3IER - 0xE007 C004 when DLAB = 0)4274.5 UARTn Interrupt Identification Register (U0IIR - 0xE000 C008, U2IIR - 0xE007 8008, U3IIR - 0x7008 C008, Read Only)4284.6 UARTn FIFO Control Register (U0FCR - 0xE000 C008, U2FCR - 0xE007 8008, U3FCR - 0xE007 C008, Write Only)4304.7 UARTn Line Control Register (U0LCR - 0xE000 C00C, U2LCR - 0xE007 800C, U3LCR - 0xE007 C00C)4304.8 UARTn Line Status Register (U0LSR - 0xE000 C014, U2LSR - 0xE007 8014, U3LSR - 0xE007 C014, Read Only)4314.9 UARTn Scratch Pad Register (U0SCR - 0xE000 C01C, U2SCR - 0xE007 801C U3SCR - 0xE007 C01C)4334.10 UARTn Auto-baud Control Register (U0ACR - 0xE000 C020, U2ACR - 0xE007 8020, U3ACR - 0xE007 C020)4334.11 IrDA Control Register for UART3 Only (U3ICR - 0xE007 C024)4364.12 UARTn Fractional Divider Register (U0FDR - 0xE000 C028, U2FDR - 0xE007 8028, U3FDR - 0xE007 C028)4374.13 UARTn Transmit Enable Register (U0TER - 0xE000 C030, U2TER - 0xE007 8030, U3TER - 0xE007 C030)4405. Architecture441Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter (UART) 14431. Basic configuration4432. Features4433. Pin description4444. Register description4444.1 UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0 Read Only)4474.2 UART1 Transmitter Holding Register (U1THR - 0xE001 0000 when DLAB = 0, Write Only)4474.3 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0xE001 0000 and U1DLM - 0xE001 0004, when DLAB = 1)4474.4 UART1 Interrupt Enable Register (U1IER - 0xE001 0004, when DLAB = 0)4484.5 UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read Only)4494.6 UART1 FIFO Control Register (U1FCR - 0xE001 0008, Write Only)4524.7 UART1 Line Control Register (U1LCR - 0xE001 000C)4524.8 UART1 Modem Control Register (U1MCR - 0xE001 0010)4534.9 Auto-flow control4544.10 UART1 Line Status Register (U1LSR - 0xE001 0014, Read Only)4564.11 UART1 Modem Status Register (U1MSR - 0xE001 0018)4574.12 UART1 Scratch Pad Register (U1SCR - 0xE001 001C)4584.13 UART1 Auto-baud Control Register (U1ACR - 0xE001 0020)4584.14 Auto-baud4594.15 Auto-baud modes4604.16 UART1 Fractional Divider Register (U1FDR - 0xE001 0028)4614.17 UART1 Transmit Enable Register (U1TER - 0xE001 0030)4645. Architecture465Chapter 18: LPC24XX CAN controllers CAN1/24671. How to read this chapter4672. Basic configuration4673. CAN controllers4674. Features4684.1 General CAN features4684.2 CAN controller features4684.3 Acceptance filter features4685. Pin description4686. CAN controller architecture4696.1 APB Interface Block (AIB)4696.2 Interface Management Logic (IML)4696.3 Transmit Buffers (TXB)4706.4 Receive Buffer (RXB)4706.5 Error Management Logic (EML)4716.6 Bit Timing Logic (BTL)4716.7 Bit Stream Processor (BSP)4716.8 CAN controller self-tests4717. Memory map of the CAN block4738. Register description4738.1 Mode Register (CAN1MOD - 0xE004 4000, CAN2MOD - 0xE004 8000)4758.2 Command Register (CAN1CMR - 0xE004 x004, CAN2CMR - 0xE004 8004)4768.3 Global Status Register (CAN1GSR - 0xE004 x008, CAN2GSR - 0xE004 8008)4788.4 Interrupt and Capture Register (CAN1ICR - 0xE004 400C, CAN2ICR - 0xE004 800C)4808.5 Interrupt Enable Register (CAN1IER - 0xE004 4010, CAN2IER - 0xE004 8010)4848.6 Bus Timing Register (CAN1BTR - 0xE004 4014, CAN2BTR - 0xE004 8014)4858.7 Error Warning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL - 0xE004 8018)4878.8 Status Register (CAN1SR - 0xE004 401C, CAN2SR - 0xE004 801C)4878.9 Receive Frame Status Register (CAN1RFS - 0xE004 4020, CAN2RFS - 0xE004 8020)4898.10 Receive Identifier Register (CAN1RID - 0xE004 4024, CAN2RID - 0xE004 8024)4908.11 Receive Data Register A (CAN1RDA - 0xE004 4028, CAN2RDA - 0xE004 8028)4908.12 Receive Data Register B (CAN1RDB - 0xE004 402C, CAN2RDB - 0xE004 802C)4918.13 Transmit Frame Information Register (CAN1TFI[1/2/3] - 0xE004 40[30/ 40/50], CAN2TFI[1/2/3] - 0xE004 80[30/40/50])4918.14 Transmit Identifier Register (CAN1TID[1/2/3] - 0xE004 40[34/44/54], CAN2TID[1/2/3] - 0xE004 80[34/44/54])4938.15 Transmit Data Register A (CAN1TDA[1/2/3] - 0xE004 40[38/48/58], CAN2TDA[1/2/3] - 0xE004 80[38/48/58])4938.16 Transmit Data Register B (CAN1TDB[1/2/3] - 0xE004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0xE004 80[3C/4C/5C])4949. CAN controller operation4949.1 Error handling4949.2 Sleep mode4949.3 Interrupts4959.4 Transmit priority49510. Centralized CAN registers49510.1 Central Transmit Status Register (CANTxSR - 0xE004 0000)49510.2 Central Receive Status Register (CANRxSR - 0xE004 0004)49610.3 Central Miscellaneous Status Register (CANMSR - 0xE004 0008)49611. Global acceptance filter49712. Acceptance filter modes49712.1 Acceptance filter Off mode49712.2 Acceptance filter Bypass mode49812.3 Acceptance filter Operating mode49812.4 FullCAN mode49813. Sections of the ID look-up table RAM49814. ID look-up table RAM49815. Acceptance filter registers50015.1 Acceptance Filter Mode Register (AFMR - 0xE003 C000)50015.2 Section configuration registers50115.3 Standard Frame Individual Start Address Register (SFF_sa - 0xE003 C004)50215.4 Standard Frame Group Start Address Register (SFF_GRP_sa - 0xE003 C008)50215.5 Extended Frame Start Address Register (EFF_sa - 0xE003 C00C)50315.6 Extended Frame Group Start Address Register (EFF_GRP_sa - 0xE003 C010)50315.7 End of AF Tables Register (ENDofTable - 0xE003 C014)50415.8 Status registers50415.9 LUT Error Address Register (LUTerrAd - 0xE003 C018)50415.10 LUT Error Register (LUTerr - 0xE003 C01C)50515.11 Global FullCANInterrupt Enable register (FCANIE - 0xE003 C020)50515.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0xE003 C024 and FCANIC1 - 0xE003 C028)50516. Configuration and search algorithm50616.1 Acceptance filter search algorithm50617. FullCAN mode50717.1 FullCAN message layout50917.2 FullCAN interrupts51117.3 Set and clear mechanism of the FullCAN interrupt51318. Examples of acceptance filter tables and ID index values51818.1 Example 1: only one section is used51818.2 Example 2: all sections are used51818.3 Example 3: more than one but not all sections are used51818.4 Configuration example 451918.5 Configuration example 551918.6 Configuration example 652018.7 Configuration example 752218.8 Look-up table programming guidelines524Chapter 19: LPC24XX SPI5261. Basic configuration5262. Features5263. SPI overview5264. SPI data transfers5265. SPI peripheral details5285.1 General information5285.2 Master operation5285.3 Slave operation5295.4 Exception conditions5296. Pin description5307. Register description5317.1 SPI Control Register (S0SPCR - 0xE002 0000)5317.2 SPI Status Register (S0SPSR - 0xE002 0004)5327.3 SPI Data Register (S0SPDR - 0xE002 0008)5337.4 SPI Clock Counter Register (S0SPCCR - 0xE002 000C)5337.5 SPI Test Control Register (SPTCR - 0xE002 0010)5337.6 SPI Test Status Register (SPTSR - 0xE002 0014)5347.7 SPI Interrupt Register (S0SPINT - 0xE002 001C)5348. Architecture534Chapter 20: LPC24XX SSP interface SSP0/15361. Basic configuration5362. Features5363. Description5364. Pin descriptions5375. Bus description5375.1 Texas Instruments synchronous serial frame format5375.2 SPI frame format5385.3 Semiconductor Microwire frame format5426. Register description5446.1 SSPn Control Register 0 (SSP0CR0 - 0xE006 8000, SSP1CR0 - 0xE003 0000)5456.2 SSPn Control Register 1 (SSP0CR1 - 0xE006 8004, SSP1CR1 - 0xE003 0004)5466.3 SSPn Data Register (SSP0DR - 0xE006 8008, SSP1DR - 0xE003 0008)5476.4 SSPn Status Register (SSP0SR - 0xE006 800C, SSP1SR - 0xE003 000C)5486.5 SSPn Clock Prescale Register (SSP0CPSR - 0xE006 8010, SSP1CPSR - 0xE003 0010)5486.6 SSPn Interrupt Mask Set/Clear Register (SSP0IMSC - 0xE006 8014, SSP1IMSC - 0xE003 0014)5486.7 SSPn Raw Interrupt Status Register (SSP0RIS - 0xE006 8018, SSP1RIS - 0xE003 0018)5496.8 SSPn Masked Interrupt Status Register (SSP0MIS - 0xE006 801C, SSP1MIS - 0xE003 001C)5496.9 SSPn Interrupt Clear Register (SSP0ICR - 0xE006 8020, SSP1ICR - 0xE003 0020)5506.10 SSPn DMA Control Register (SSP0DMACR - 0xE006 8024, SSP1DMACR - 0xE003 0024)550Chapter 21: LPC24XX SD/MMC card interface5511. Basic configuration5512. Introduction5513. Features of the MCI5514. SD/MMC card interface pin description5515. Functional overview5525.1 Mutimedia card5525.2 Secure digital memory card5525.2.1 Secure digital memory card bus signals5535.3 MCI adapter5535.3.1 Adapter register block5545.3.2 Control unit5545.3.3 Command path5545.3.4 Command path state machine5545.3.5 Command format5565.3.6 Data path5575.3.7 Data path state machine5575.3.8 Data counter5595.3.9 Bus mode5605.3.10 CRC Token status5605.3.11 Status flags5615.3.12 CRC generator5615.3.13 Data FIFO5615.3.14 Transmit FIFO5625.3.15 Receive FIFO5625.3.16 APB interfaces5635.3.17 Interrupt logic5636. Register description5636.1 Power Control Register (MCI Power - 0xE008 C000)5646.2 Clock Control Register (MCIClock - 0xE008 C004)5646.3 Argument Register (MCIArgument - 0xE008 C008)5656.4 Command Register (MCICommand - 0xE008 C00C)5656.5 Command Response Register (MCIRespCommand - 0xE008 C010)5666.6 Response Registers (MCIResponse0-3 - 0xE008 C014, E008 C018, E008 C01C and E008 C020)5666.7 Data Timer Register (MCIDataTimer - 0xE008 C024)5676.8 Data Length Register (MCIDataLength - 0xE008 C028)5676.9 Data Control Register (MCIDataCtrl - 0xE008 C02C)5686.10 Data Counter Register (MCIDataCnt - 0xE008 C030)5686.11 Status Register (MCIStatus - 0xE008 C034)5696.12 Clear Register (MCIClear - 0xE008 C038)5706.13 Interrupt Mask Registers (MCIMask0 - 0xE008 C03C)5706.14 FIFO Counter Register (MCIFifoCnt - 0xE008 C048)5716.15 Data FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)571Chapter 22: LPC24XX I2C interfaces I2C0/1/25721. Basic configuration5722. Features5723. Applications5724. Description5725. Pin description5746. I2C operating modes5746.1 Master Transmitter mode5746.2 Master Receiver mode5756.3 Slave Receiver mode5766.4 Slave Transmitter mode5777. I2C implementation and operation5777.1 Input filters and output stages5777.2 Address Register I2ADDR5797.3 Comparator5797.4 Shift register I2DAT5797.5 Arbitration and synchronization logic5797.6 Serial clock generator5807.7 Timing and control5807.8 Control register I2CONSET and I2CONCLR5807.9 Status decoder and status register5818. Register description5818.1 I2C Control Set Register (I2C[0/1/2]CONSET: 0xE001 C000, 0xE005 C000, 0xE008 0000)5828.2 I2C Control Clear Register (I2C[0/1/2]CONCLR: 0xE001 C018, 0xE005 C018, 0xE008 0018)5848.3 I2C Status Register (I2C[0/1/2]STAT - 0xE001 C004, 0xE005 C004, 0xE008 0004)5848.4 I2C Data Register (I2C[0/1/2]DAT - 0xE001 C008, 0xE005 C008, 0xE008 0008)5858.5 I2C Slave Address Register (I2C[0/1/2]ADR - 0xE001 C00C, 0xE005 C00C, 0xE008 000C)5858.6 I2C SCL High Duty Cycle Register (I2C[0/1/2]SCLH - 0xE001 C010, 0xE005 C010, 0xE008 0010)5858.7 I2C SCL Low Duty Cycle Register (I2C[0/1/2]SCLL - 0xE001 C014, 0xE005 C014, 0xE008 0014)5858.8 Selecting the appropriate I2C data rate and duty cycle5859. Details of I2C operating modes5869.1 Master Transmitter mode5879.2 Master Receiver mode5889.3 Slave Receiver mode5889.4 Slave Transmitter mode5939.5 Miscellaneous states5999.6 Some special cases6009.7 Simultaneous repeated START conditions from two masters6009.8 Data transfer after loss of arbitration6009.9 Forced access to the I2C bus6009.10 I2C Bus obstructed by a Low level on SCL or SDA6019.11 Bus error6019.12 I2C State service routines60210. Software example60310.1 Initialization routine60310.2 Start master transmit function60310.3 Start master receive function60310.4 I2C interrupt routine60410.5 Non mode specific states60410.6 Master states60410.7 Master Transmitter states60510.8 Master Receive states60610.9 Slave Receiver states60710.10 Slave Transmitter States609Chapter 23: LPC24XX I2S interface6111. Basic configuration6112. Features6113. Description6114. Pin descriptions6125. Register description6135.1 Digital Audio Output Register (I2SDAO - 0xE008 8000)6145.2 Digital Audio Input Register (I2SDAI - 0xE008 8004)6145.3 Transmit FIFO Register (I2STXFIFO - 0xE008 8008)6155.4 Receive FIFO Register (I2SRXFIFO - 0xE008 800C)6155.5 Status Feedback Register (I2SSTATE - 0xE008 8010)6155.6 DMA Configuration Register 1 (I2SDMA1 - 0xE008 8014)6165.7 DMA Configuration Register 2 (I2SDMA2 - 0xE008 8018)6165.8 Interrupt Request Control Register (I2SIRQ - 0xE008 801C)6165.9 Transmit Clock Rate Register (I2STXRATE - 0xE008 8020)6175.10 Receive Clock Rate Register (I2SRXRATE - 0xE008 8024)6176. I2S transmit and receive interfaces6177. FIFO controller618Chapter 24: LPC24XX Timer0/1/2/36211. Basic configuration6212. Features6213. Applications6214. Description6225. Pin description6225.1 Multiple CAP and MAT pins6226. Register description6226.1 Interrupt Register (T[0/1/2/3]IR - 0xE000 4000, 0xE000 8000, 0xE007 0000, 0xE007 4000)6246.2 Timer Control Register (T[0/1/2/3]CR - 0xE000 4004, 0xE000 8004, 0xE007 0004, 0xE007 4004)6246.3 Count Control Register (T[0/1/2/3]CTCR - 0xE000 4070, 0xE000 8070, 0xE007 0070, 0xE007 4070)6256.4 Timer Counter registers (T0TC - T3TC, 0xE000 4008, 0xE000 8008, 0xE007 0008, 0xE007 4008)6266.5 Prescale register (T0PR - T3PR, 0xE000 400C, 0xE000 800C, 0xE007 000C, 0xE007 400C)6266.6 Prescale Counter register (T0PC - T3PC, 0xE000 4010, 0xE000 8010, 0xE007 0010, 0xE007 4010)6266.7 Match Registers (MR0 - MR3)6266.8 Match Control Register (T[0/1/2/3]MCR - 0xE000 4014, 0xE000 8014, 0xE007 0014, 0xE007 4014)6276.9 Capture Registers (CR0 - CR3)6286.10 Capture Control Register (T[0/1/2/3]CCR - 0xE000 4028, 0xE000 8028, 0xE007 0028, 0xE007 4028)6286.11 External Match Register (T[0/1/2/3]EMR - 0xE000 403C, 0xE000 803C, 0xE007 003C, 0xE007 403C)6297. Example timer operation6308. Architecture630Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM16321. Basic configuration6322. Features6323. Description6333.1 Rules for single edge controlled PWM outputs6353.2 Rules for double edge controlled PWM outputs6353.3 Summary of differences from the standard timer block6354. Pin description6375. PWM base addresses6376. Register description6376.1 PWM Interrupt Register (PWM0IR - 0xE001 4000 and PWM1IR 0xE001 8000)6396.2 PWM Timer Control Register (PWM0TCR - 0xE001 4004 and PWM1TCR 0xE001 8004)6406.3 PWM Count Control Register (PWM0CTCR - 0xE001 4070 and PWM1CTCR 0xE001 8070)6416.4 PWM Match Control Register (PWM0MCR - 0xE001 4014 and PWM1MCR 0xE001 8014)6416.5 PWM Capture Control Register (PWM0CCR - 0xE001 4028 and PWM1CCR 0xE001 8028)6436.6 PWM Control Registers (PWM0PCR - 0xE001 404C and PWM1PCR 0xE001 804C)6446.7 PWM Latch Enable Register (PWM0LER - 0xE001 4050 and PWM1LER 0xE001 8050)645Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM6471. Basic configuration6472. Features6473. Description6474. Architecture6485. Pin description6486. Register description6496.1 RTC interrupts6506.2 Miscellaneous register group6506.3 Consolidated time registers6546.4 Time Counter Group6557. Alarm register group6568. Alarm output6569. RTC usage notes65610. RTC clock generation65710.1 Reference Clock Divider (Prescaler)65710.2 Prescaler Integer Register (PREINT - 0xE002 4080)65710.3 Prescaler Fraction Register (PREFRAC - 0xE002 4084)65810.4 Example of Prescaler Usage65810.5 Prescaler operation65911. Battery RAM66012. RTC external 32 kHz oscillator component selection660Chapter 27: LPC24XX WatchDog Timer (WDT)6621. Features6622. Applications6623. Description6624. Register description6634.1 Watchdog Mode Register (WDMOD - 0xE000 0000)6634.2 Watchdog Timer Constant Register (WDTC - 0xE000 0004)6644.3 Watchdog Feed Register (WDFEED - 0xE000 0008)6644.4 Watchdog Timer Value Register (WDTV - 0xE000 000C)6654.5 Watchdog Timer Clock Source Selection Register (WDCLKSEL - 0xE000 0010)6655. Block diagram666Chapter 28: LPC24XX Analog-to Digital Converter (ADC)6671. Basic configuration6672. Features6673. Description6674. Pin description6675. Register description6685.1 A/D Control Register (AD0CR - 0xE003 4000)6695.2 A/D Global Data Register (AD0GDR - 0xE003 4004)6705.3 A/D Status Register (AD0STAT - 0xE003 4030)6715.4 A/D Interrupt Enable Register (AD0INTEN - 0xE003 400C)6725.5 A/D Data Registers (AD0DR0 to AD0DR7 - 0xE003 4010 to 0xE003 402C)6726. Operation6736.1 Hardware-triggered conversion6736.2 Interrupts6736.3 Accuracy vs. digital receiver673Chapter 29: LPC24XX Digital-to Analog Converter (DAC)6741. Basic configuration6742. Features6743. Pin description6744. Register description (DACR - 0xE006 C000)6745. Operation675Chapter 30: LPC24XX Flash memory programming firmware6761. How to read this chapter6762. Flash boot loader6763. Features6764. Applications6765. Description6765.1 Memory map after any reset6775.2 Communication protocol6786. Boot process flowchart6807. Sector numbers6818. Code Read Protection (CRP)6829. ISP commands6839.1 Unlock <Unlock code>6849.2 Set Baud Rate <Baud Rate> <stop bit>6849.3 Echo <setting>6859.4 Write to RAM <start address> <number of bytes>6859.5 Read Memory <address> <no. of bytes>6859.6 Prepare sector(s) for write operation <start sector number> <end sector number>6869.7 Copy RAM to Flash <Flash address> <RAM address> <no of bytes>6879.8 Go <address> <mode>6879.9 Erase sector(s) <start sector number> <end sector number>6889.10 Blank check sector(s) <sector number> <end sector number>6889.11 Read Part Identification number6889.12 Read Boot code version number6899.13 Compare <address1> <address2> <no of bytes>6899.14 ISP Return Codes68910. IAP commands69010.1 Prepare sector(s) for write operation69210.2 Copy RAM to Flash69310.3 Erase Sector(s)69410.4 Blank check sector(s)69410.5 Read Part Identification number69410.6 Read Boot code version number69510.7 Compare <address1> <address2> <no of bytes>69510.8 Reinvoke ISP69510.9 IAP Status Codes69611. JTAG Flash programming interface696Chapter 31: LPC24XX On-chip bootloader for flashless parts6971. How to read this chapter6972. Features6973. Applications6974. Description6974.1 Memory map after any reset6984.2 Communication protocol6985. Boot process flowchart7006. ISP commands7016.1 Unlock <Unlock code>7016.2 Set Baud Rate <Baud Rate> <stop bit>7016.3 Echo <setting>7026.4 Write to RAM <start address> <number of bytes>7026.5 Read Memory <address> <no. of bytes>7036.6 Go <address> <mode>7046.7 Read Part Identification number7046.8 Read Boot code version number7046.9 Compare <address1> <address2> <no of bytes>7056.10 ISP Return Codes7057. IAP commands7067.1 Read Part Identification number7087.2 Read Boot code version number7087.3 Compare <address1> <address2> <no of bytes>7097.4 Reinvoke ISP7097.5 IAP Status Codes709Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller7111. Basic configuration7112. Introduction7113. Features of the GPDMA7114. Functional overview7124.1 Memory regions accessible by the GPDMA7124.2 GPDMA functional description7124.3 DMA system connections7175. Programming the GPDMA7185.1 Enabling the GPDMA7185.2 Disabling the GPDMA7185.3 Enabling a DMA channel7195.4 Disabling a DMA channel7195.5 Disabling a DMA channel without losing data in the FIFO7195.6 Setup a new DMA transfer7195.7 Disabling a DMA channel and losing data in the FIFO7195.8 Halting a DMA transfer7195.9 Programming a DMA channel7206. Register description7206.1 General GPDMA registers7216.2 Channel registers7277. Address generation7338. Scatter/Gather7338.1 Linked List Items7338.2 Programming the GPDMA for scatter/gather DMA7348.3 Example of scatter/gather DMA7349. Interrupt requests7359.1 Hardware interrupt sequence flow7369.2 Interrupt polling sequence flow73610. GPDMA data flow73610.1 Peripheral-to-memory, or Memory-to-peripheral DMA flow73710.2 Peripheral-to-peripheral DMA flow73710.3 Memory-to-memory DMA flow73811. Flow control739Chapter 33: LPC24XX EmbeddedICE7401. Features7402. Applications7403. Description7404. Pin description7415. JTAG function select7426. Register description7427. Block diagram742Chapter 34: LPC24XX Embedded Trace Module (ETM)7441. Features7442. Applications7443. Description7443.1 ETM configuration7444. Pin description7455. Register description7456. Reset state of multiplexed pins7467. Block diagram747Chapter 35: LPC24XX RealMonitor7481. Features7482. Applications7483. Description7483.1 RealMonitor components7493.2 How RealMonitor works7504. How to enable RealMonitor7514.1 Adding stacks7514.2 IRQ mode7514.3 Undef mode7514.4 SVC mode7514.5 Prefetch Abort mode7524.6 Data Abort mode7524.7 User/System mode7524.8 FIQ mode7524.9 Handling exceptions7524.10 RMTarget initialization7534.11 Code example7535. RealMonitor build options756Chapter 36: LPC24XX Supplementary information7591. Abbreviations7592. Legal information7602.1 Definitions7602.2 Disclaimers7602.3 Trademarks7603. Tables7614. Figures7735. Contents775Размер: 4,6 МБСтраницы: 792Язык: EnglishПросмотреть
