Инструкции для Renesas M16C/6NK

Содержание

• Keep safety first in your circuit designs!

  2
• Notes regarding these materials

  2
• How to Use This Manual

  3
  • 1. Introduction

    3
  • 2. Register Diagram

    3
  • 3. M16C Family Documents

    4
• Table of Contents

  5
• SFR Page Reference

  11
• 1. Overview

  19
  • 1.1 Applications

    19
  • 1.2 Performance Outline

    20
  • 1.3 Block Diagram

    22
  • 1.4 Product List

    23
  • 1.5 Pin Configuration

    24
  • 1.6 Pin Description

    26
• 2. Central Processing Unit (CPU)

  28
  • 2.1 Data Registers (R0, R1, R2, and R3)

    28
  • 2.2 Address Registers (A0 and A1)

    28
  • 2.3 Frame Base Register (FB)

    29
  • 2.4 Interrupt Table Register (INTB)

    29
  • 2.5 Program Counter (PC)

    29
  • 2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

    29
  • 2.7 Static Base Register (SB)

    29
  • 2.8 Flag Register (FLG)

    29
    • 2.8.1 Carry Flag (C Flag)

      29
    • 2.8.2 Debug Flag (D Flag)

      29
    • 2.8.3 Zero Flag (Z Flag)

      29
    • 2.8.4 Sign Flag (S Flag)

      29
    • 2.8.5 Register Bank Select Flag (B Flag)

      29
    • 2.8.6 Overflow Flag (O Flag)

      29
    • 2.8.7 Interrupt Enable Flag (I Flag)

      29
    • 2.8.8 Stack Pointer Select Flag (U Flag)

      29
    • 2.8.9 Processor Interrupt Priority Level (IPL)

      29
    • 2.8.10 Reserved Area

      29
• 3. Memory

  30
• 4. Special Function Register (SFR)

  31
• 5. Reset

  47
  • 5.1 Hardware Reset

    47
    • 5.1.1 Reset on a Stable Supply Voltage

      47
    • 5.1.2 Power-on Reset

      47
  • 5.2 Software Reset

    47
  • 5.3 Watchdog Timer Reset

    47
  • 5.4 Oscillation Stop Detection Reset

    47
• 6. Processor Mode

  50
• 7. Clock Generating Circuit

  53
  • 7.1 Types of Clock Generating Circuit

    53
    • 7.1.1 Main Clock

      61
    • 7.1.2 Sub Clock

      62
    • 7.1.3 On-chip Oscillator Clock

      63
    • 7.1.4 PLL Clock

      63
  • 7.2 CPU Clock and Peripheral Function Clock

    65
    • 7.2.1 CPU Clock and BCLK

      65
    • 7.2.2 Peripheral Function Clock

      65
  • 7.3 Clock Output Function

    65
  • 7.4 Power Control

    66
    • 7.4.1 Normal Operation Mode

      66
    • 7.4.2 Wait Mode

      68
    • 7.4.3 Stop Mode

      70
  • 7.5 Oscillation Stop and Re-oscillation Detection Function

    75
    • 7.5.1 Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset)

      75
    • 7.5.2 Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt)

      75
    • 7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function

      76
• 8. Protection

  77
• 9. Interrupt

  78
  • 9.1 Type of Interrupts

    78
  • 9.2 Software Interrupts

    79
    • 9.2.1 Undefined Instruction Interrupt

      79
    • 9.2.2 Overflow Interrupt

      79
    • 9.2.3 BRK Interrupt

      79
    • 9.2.4 INT Instruction Interrupt

      79
  • 9.3 Hardware Interrupts

    80
    • 9.3.1 Special Interrupts

      80
    • 9.3.2 Peripheral Function Interrupts

      80
  • 9.4 Interrupts and Interrupt Vector

    81
    • 9.4.1 Fixed Vector Tables

      81
    • 9.4.2 Relocatable Vector Tables

      81
  • 9.5 Interrupt Control

    83
    • 9.5.1 I Flag

      85
    • 9.5.2 IR Bit

      85
    • 9.5.3 ILVL2 to ILVL0 Bits and IPL

      85
    • 9.5.4 Interrupt Sequence

      86
    • 9.5.5 Interrupt Response Time

      87
    • 9.5.6 Variation of IPL when Interrupt Request is Accepted

      87
    • 9.5.7 Saving Registers

      88
    • 9.5.8 Returning from an Interrupt Routine

      89
    • 9.5.9 Interrupt Priority

      89
    • 9.5.10 Interrupt Priority Resolution Circuit

      89
  • 9.6 INT Interrupt

    91
  • 9.7 NMI Interrupt

    95
  • 9.8 Key Input Interrupt

    95
  • 9.9 CAN0/1 Wake-up Interrupt

    95
  • 9.10 Address Match Interrupt

    96
• 10. Watchdog Timer

  98
  • 10.1 Count Source Protective Mode

    99
• 11. DMAC

  100
  • 11.1 Transfer Cycle

    105
    • 11.1.1 Effect of Source and Destination Addresses

      105
    • 11.1.2 Effect of Software Wait

      105
  • 11.2 DMA Transfer Cycles

    107
  • 11.3 DMA Enable

    108
  • 11.4 DMA Request

    108
  • 11.5 Channel Priority and DMA Transfer Timing

    109
• 12. Timers

  110
  • 12.1 Timer A

    112
    • 12.1.1 Timer Mode

      116
    • 12.1.2 Event Counter Mode

      117
    • 12.1.3 One-shot Timer Mode

      122
    • 12.1.4 Pulse Width Modulation (PWM) Mode

      124
  • 12.2 Timer B

    127
    • 12.2.1 Timer Mode

      130
    • 12.2.2 Event Counter Mode

      131
    • 12.2.3 Pulse Period and Pulse Width Measurement Mode

      132
• 13. Three-Phase Motor Control Timer Function

  135
• 14. Serial I/O

  146
  • 14.1 UARTi

    146
    • 14.1.1 Clock Synchronous Serial I/O Mode

      156
    • 14.1.2 Clock Asynchronous Serial I/O (UART) Mode

      164
    • 14.1.3 Special Mode 1 (I2C Mode)

      172
    • 14.1.4 Special Mode 2

      181
    • 14.1.5 Special Mode 3 (IE Mode)

      186
    • 14.1.6 Special Mode 4 (SIM Mode) (UART2)

      188
  • 14.2 SI/Oi

    193
    • 14.2.1 SI/Oi Operation Timing

      197
    • 14.2.2 CLK Polarity Selection

      197
    • 14.2.3 Functions for Setting an SOUTi Initial Value

      198
• 15. A/D Converter

  199
  • 15.1 Mode Description

    203
    • 15.1.1 One-shot Mode

      203
    • 15.1.2 Repeat Mode

      205
    • 15.1.3 Single Sweep Mode

      207
    • 15.1.4 Repeat Sweep Mode 0

      209
    • 15.1.5 Repeat Sweep Mode 1

      211
  • 15.2 Function

    213
    • 15.2.1 Resolution Select Function

      213
    • 15.2.2 Sample and Hold

      213
    • 15.2.3 Extended Analog Input Pins

      213
    • 15.2.4 External Operation Amplifier (Op-Amp) Connection Mode

      213
    • 15.2.5 Current Consumption Reducing Function

      214
    • 15.2.6 Output Impedance of Sensor under A/D Conversion

      214
• 16. D/A Converter

  216
• 17. CRC Calculation

  218
• 18. CAN Module

  220
  • 18.1 CAN Module-Related Registers

    221
    • 18.1.1 CAN Message Box

      221
    • 18.1.2 Acceptance Mask Registers

      221
    • 18.1.3 CAN SFR Registers

      221
  • 18.2 CANi Message Box

    222
  • 18.3 Acceptance Mask Registers

    224
  • 18.4 CAN SFR Registers

    225
  • 18.5 Operational Modes

    231
    • 18.5.1 CAN Reset/Initialization Mode

      231
    • 18.5.2 CAN Operation Mode

      232
    • 18.5.3 CAN Sleep Mode

      232
    • 18.5.4 CAN Interface Sleep Mode

      232
    • 18.5.5 Bus Off State

      233
  • 18.6 Configuration CAN Module System Clock

    234
  • 18.7 Bit Timing Configuration

    234
  • 18.8 Bit-rate

    235
  • 18.9 Acceptance Filtering Function and Masking Function

    236
  • 18.10 Acceptance Filter Support Unit (ASU)

    237
  • 18.11 Basic CAN Mode

    238
  • 18.12 Return from Bus off Function

    239
  • 18.13 Time Stamp Counter and Time Stamp Function

    239
  • 18.14 Listen-Only Mode

    239
  • 18.15 Reception and Transmission

    240
    • 18.15.1 Reception

      241
    • 18.15.2 Transmission

      242
  • 18.16 CAN Interrupt

    243
• 19. Programmable I/O Ports

  244
  • 19.1 PDi Register

    245
  • 19.2 Pi Register, PC14 Register

    245
  • 19.3 PURj Register

    245
  • 19.4 PCR Register

    245
• 20. Flash Memory Version

  256
  • 20.1 Memory Map

    258
    • 20.1.1 Boot Mode

      258
  • 20.2 Functions to Prevent Flash Memory from Rewriting

    258
    • 20.2.1 ROM Code Protect Function

      258
    • 20.2.2 ID Code Check Function

      258
  • 20.3 CPU Rewrite Mode

    260
    • 20.3.1 EW0 Mode

      261
    • 20.3.2 EW1 Mode

      261
    • 20.3.3 FMR0, FMR1 Registers

      262
    • 20.3.4 Precautions on CPU Rewrite Mode

      266
    • 20.3.5 Software Commands

      268
    • 20.3.6 Data Protect Function

      273
    • 20.3.7 Status Register (SRD Registser)

      273
    • 20.3.8 Full Status Check

      275
  • 20.4 Standard Serial I/O Mode

    277
    • 20.4.1 ID Code Check Function

      277
    • 20.4.2 Example of Circuit Application in Standard Serial I/O Mode

      281
  • 20.5 Parallel I/O Mode

    282
    • 20.5.1 User ROM and Boot ROM Areas

      282
    • 20.5.2 ROM Code Protect Function

      282
  • 20.6 CAN I/O Mode

    283
    • 20.6.1 ID Code Check Function

      283
    • 20.6.2 Example of Circuit Application in CAN I/O Mode

      286
• 21. Electrical Characteristics

  287
• 22. Usage Precaution

  297
  • 22.1 SFR

    297
  • 22.2 External Clock

    298
  • 22.3 PLL Frequency Synthesizer

    299
  • 22.4 Power Control

    300
  • 22.5 Oscillation Stop, Re-oscillation Detection Function

    302
  • 22.6 Protection

    303
  • 22.7 Interrupt

    304
    • 22.7.1 Reading Address 00000h

      304
    • 22.7.2 Setting SP

      304
    • 22.7.3 NMI Interrupt

      304
    • 22.7.4 Changing Interrupt Generate Factor

      305
    • 22.7.5 INT Interrupt

      305
    • 22.7.6 Rewrite Interrupt Control Register

      306
    • 22.7.7 Watchdog Timer Interrupt

      306
  • 22.8 DMAC

    307
    • 22.8.1 Write to DMAE Bit in DMiCON Register

      307
  • 22.9 Timers

    308
    • 22.9.1 Timer A

      308
    • 22.9.2 Timer B

      312
  • 22.10 Thee-Phase Motor Control Timer Function

    314
  • 22.11 Serial I/O

    315
    • 22.11.1 Clock Synchronous Serial I/O Mode

      315
    • 22.11.2 Special Modes

      316
    • 22.11.3 SI/Oi

      317
  • 22.12 A/D Converter

    318
  • 22.13 CAN Module

    320
    • 22.13.1 Reading CiSTR Register

      320
    • 22.13.2 Performing CAN Configuration

      322
    • 22.13.3 Suggestions to Reduce Power Consumption

      323
    • 22.13.4 CAN Transceiver in Boot Mode

      324
  • 22.14 Programmable I/O Ports

    325
  • 22.15 Dedicated Input Pin

    326
  • 22.16 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers

    327
  • 22.17 Mask ROM Version

    328
  • 22.18 Flash Memory Version

    329
    • 22.18.1 Functions to Prevent Flash Memory from Rewriting

      329
    • 22.18.2 Stop Mode

      329
    • 22.18.3 Wait Mode

      329
    • 22.18.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode

      329
    • 22.18.5 Writing Command and Data

      329
    • 22.18.6 Program Command

      329
    • 22.18.7 Lock Bit Program Command

      329
    • 22.18.8 Operation Speed

      330
    • 22.18.9 Prohibited Instructions

      330
    • 22.18.10 Interrupt

      330
    • 22.18.11 How to Access

      330
    • 22.18.12 Rewriting in User ROM Area

      330
    • 22.18.13 DMA Transfer

      330
  • 22.19 Flash Memory Programming Using Boot Program

    331
    • 22.19.1 Programming Using Serial I/O Mode

      331
    • 22.19.2 Programming Using CAN I/O Mode

      331
  • 22.20 Noise

    332
• Appendix 1. Package Dimensions

  333
• Register Index

  335
  • A

    335
    • AD0 to AD7

      202
    • ADCON0, ADCON1

      201
      • ADCON0, ADCON1 (One-shot Mode)

        204
      • ADCON0, ADCON1 (Repeat Mode)

        206
      • ADCON0, ADCON1 (Single Sweep Mode)

        208
      • ADCON0, ADCON1 (Repeat Sweep Mode 0)

        210
      • ADCON0, ADCON1 (Repeat Sweep Mode 1)

        212
    • ADCON2

      202
    • ADIC

      83
    • AIER

      97
    • AIER2

      97
  • C

    335
    • C01ERRIC

      83
    • C01WKIC

      83
    • C0AFS, C1AFS

      230
    • C0CONR, C1CONR

      229
    • C0CTLR, C1CTLR

      226
    • C0GMR, C1GMR

      224
    • C0ICR, C1ICR

      228
    • C0IDR, C1IDR

      228
    • C0LMAR, C1LMAR

      224
    • C0LMBR, C1LMBR

      224
    • C0MCTL0 to C0MCTL15, C1MCTL0 to C1MCTL15

      225
    • C0RECIC

      83
    • C0RECR, C1RECR

      230
    • C0SSTR, C1SSTR

      228
    • C0STR, C1STR

      227
    • C0TECR, C1TECR

      230
    • C0TRMIC

      83
    • C0TSR, C1TSR

      230
    • C1RECIC

      84
    • C1TRMIC

      84
    • CAN0/1 Slot 0 to 15_1

      222
    • CAN0/1 Slot 0 to 15_2

      223
    • CCLKR

      59
    • CM0

      55
    • CM1

      56
    • CM2

      57
    • CPSRF (Timer A)

      115
    • CPSRF (Timer B)

      129
    • CRCD

      218
    • CRCIN

      218
  • D

    335
    • DA0, DA1

      217
    • DACON

      217
    • DAR0, DAR1

      104
    • DM0CON, DM1CON

      103
    • DM0IC,DM1IC

      83
    • DM0SL

      102
    • DM1SL

      103
    • DTT

      139
  • F

    335
    • FMR0

      262
    • FMR1

      262
  • I

    335
    • ICTB2

      141
    • IDB0, IDB1

      139
    • IFSR0

      92
    • IFSR1

      93
    • IFSR2

      94
    • INT0IC to INT8IC

      84
    • INVC0

      137
    • INVC1

      138
  • K

    335
    • KUPIC

      83
  • O

    335
    • ONSF

      115
  • P

    335
    • P0 to P13

      252
    • PC14

      252
    • PCLKR

      58
    • PCR

      254
    • PD0 to PD13

      251
    • PLC0

      60
    • PM0

      50
    • PM1

      51
    • PM2

      59
    • PRCR

      77
    • PUR0 to PUR2

      253
    • PUR3

      254
  • R

    335
    • RMAD0 to RMAD3

      97
    • ROMCP

      259
  • S

    335
    • S0TIC to S2TIC

      83
    • S0RIC to S2RIC

      83
    • S3456TRR

      195
    • S3BRG to S6BRG

      194
    • S3C to S6C

      194
    • S3IC, S4IC

      84
    • S3TRR to S6TRR

      194
    • S5IC, S6IC

      83
    • SAR0, SAR1

      104
  • T

    335
    • TA0 to TA4

      113
    • TA0IC,TA1IC, TA4IC

      83
    • TA0MR to TA4MR

      113
      • TA0MR to TA4MR (Timer Mode)

        116
      • TA0MR to TA4MR (Event Counter Mode_not using two-phase pulse signal processing)

        118
      • TA2MR to TA4MR (Event Counter Mode_using two-phase pulse signal processing)

        120
      • TA0MR to TA4MR (One-shot Timer Mode)

        123
      • TA0MR to TA4MR (Puslse Width Modulation Mode)

        125
      • TA1MR,TA2MR,TA4MR (Three-Phase Motor Control Timer Function)

        143
    • TA1,TA2,TA4 (Three-Phase Motor Control Timer Function)

      140
    • TA11,TA21,TA41 (Three-Phase Motor Control Timer Function)

      140
    • TA2IC, TA3IC

      84
    • TABSR (Timer A)

      114
    • TABSR (Timer B)

      129
    • TABSR (Three-Phase Motor Control Timer Function)

      142
    • TB0 to TB5

      128
    • TB0MR to TB5MR

      128
      • TB0MR to TB5MR (Timer Mode)

        130
      • TB0MR to TB5MR (Event Counter Mode)

        131
      • TB0MR to TB5MR (Pulse Period / Pulse Width Measurement Mode)

        133
    • TB0IC, TB2IC to TB5IC

      83
    • TB1IC

      84
    • TB2 (Three-Phase Motor Control Timer Function)

      140
    • TB2MR (Three-Phase Motor Control Timer Function)

      143
    • TB2SC

      141
    • TBSR

      129
    • TCR0, TCR1

      104
    • TRGSR (Timer A)

      115
    • TRGSR (Three-Phase Motor Control Timer Function)

      142
  • U

    335
    • U0BCNIC to U2BCNIC

      83
    • U0BRG to U2BRG

      150
    • U0C0 to U2C0

      151
    • U0C1 to U2C1

      152
    • U0MR to U2MR

      151
    • U0RB to U2RB

      150
    • U0SMR to U2SMR

      153
    • U0SMR2 to U2SMR2

      154
    • U0SMR3 to U2SMR3

      154
    • U0SMR4 to U2SMR4

      155
    • U0TB to U2TB

      150
    • UCON

      153
    • UDF

      114
  • W

    336
    • WDC

      99
    • WDTS

      99
• REVISION HISTORY

  337