Справочник ПользователяСодержаниеChapter 1 Introduction91.1 General Terms and Conventions91.2 General Description9Figure 1.1 LAN8710/LAN8710i System Block Diagram101.3 Architectural Overview101.3.1 Configuration10Figure 1.2 LAN8710/LAN8710i Architectural Overview11Chapter 2 Pin Configuration122.1 Package Pin-out Diagram and Signal Table12Figure 2.1 LAN8710/LAN8710i 32-QFN Pin Assignments (TOP VIEW)12Table 2.1 LAN8710/LAN8710i 32-PIN QFN Pinout13Chapter 3 Pin Description14Table 3.1 Buffer Types143.1 MAC Interface Signals14Table 3.2 MII/RMII Signals 32-QFN143.2 LED Signals16Table 3.3 LED Signals 32-QFN163.3 Management Signals17Table 3.4 Management Signals 32-QFN173.4 General Signals17Table 3.5 General Signals 32-QFN173.5 10/100 Line Interface Signals17Table 3.6 10/100 Line Interface Signals 32-QFN173.6 Analog Reference18Table 3.7 Analog References 32-QFN183.7 Power Signals18Table 3.8 Power Signals 32-QFN18Chapter 4 Architecture Details194.1 Top Level Functional Architecture19Figure 4.1 100Base-TX Data Path194.2 100Base-TX Transmit194.2.1 100M Transmit Data Across the MII/RMII Interface194.2.2 4B/5B Encoding20Table 4.1 4B/5B Code Table204.2.3 Scrambling214.2.4 NRZI and MLT3 Encoding214.2.5 100M Transmit Driver214.2.6 100M Phase Lock Loop (PLL)22Figure 4.2 Receive Data Path224.3 100Base-TX Receive224.3.1 100M Receive Input224.3.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery224.3.3 NRZI and MLT-3 Decoding234.3.4 Descrambling234.3.5 Alignment234.3.6 5B/4B Decoding234.3.7 Receive Data Valid Signal23Figure 4.3 Relationship Between Received Data and Specific MII Signals244.3.8 Receiver Errors244.3.9 100M Receive Data Across the MII/RMII Interface244.4 10Base-T Transmit244.4.1 10M Transmit Data Across the MII/RMII Interface244.4.2 Manchester Encoding254.4.3 10M Transmit Drivers254.5 10Base-T Receive254.5.1 10M Receive Input and Squelch254.5.2 Manchester Decoding254.5.3 10M Receive Data Across the MII/RMII Interface264.5.4 Jabber Detection264.6 MAC Interface264.6.1 MII264.6.2 RMII264.6.3 MII vs. RMII Configuration27Table 4.2 MII/RMII Signal Mapping284.7 Auto-negotiation284.7.1 Parallel Detection304.7.2 Re-starting Auto-negotiation304.7.3 Disabling Auto-negotiation304.7.4 Half vs. Full Duplex304.8 HP Auto-MDIX Support30Figure 4.4 Direct Cable Connection vs. Cross-over Cable Connection314.9 Internal +1.2V Regulator Disable314.9.1 Disable the Internal +1.2V Regulator314.9.2 Enable the Internal +1.2V Regulator314.10 nINTSEL Strapping and LED Polarity Selection32Figure 4.5 nINTSEL Strapping on LED2324.11 REGOFF and LED Polarity Selection32Figure 4.6 REGOFF Configuration on LED1334.12 PHY Address Strapping334.13 Variable Voltage I/O334.14 Transceiver Management Control334.14.1 Serial Management Interface (SMI)33Figure 4.7 MDIO Timing and Frame Structure - READ Cycle34Figure 4.8 MDIO Timing and Frame Structure - WRITE Cycle34Chapter 5 SMI Register Mapping35Table 5.1 Control Register: Register 0 (Basic)35Table 5.2 Status Register: Register 1 (Basic)35Table 5.3 PHY ID 1 Register: Register 2 (Extended)35Table 5.4 PHY ID 2 Register: Register 3 (Extended)35Table 5.5 Auto-Negotiation Advertisement: Register 4 (Extended)36Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended)36Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended)36Table 5.8 Register 15 (Extended)36Table 5.9 Silicon Revision Register 16: Vendor-Specific36Table 5.10 Mode Control/ Status Register 17: Vendor-Specific37Table 5.11 Special Modes Register 18: Vendor-Specific37Table 5.12 Register 24: Vendor-Specific37Table 5.13 Register 25: Vendor-Specific37Table 5.14 Symbol Error Counter Register 26: Vendor-Specific37Table 5.15 Special Control/Status Indications Register 27: Vendor-Specific38Table 5.16 Special Internal Testability Control Register 28: Vendor-Specific38Table 5.17 Interrupt Source Flags Register 29: Vendor-Specific38Table 5.18 Interrupt Mask Register 30: Vendor-Specific38Table 5.19 PHY Special Control/Status Register 31: Vendor-Specific38Table 5.20 SMI Register Mapping395.1 SMI Register Format39Table 5.21 Register 0 - Basic Control40Table 5.22 Register 1 - Basic Status40Table 5.23 Register 2 - PHY Identifier 141Table 5.24 Register 3 - PHY Identifier 241Table 5.25 Register 4 - Auto Negotiation Advertisement41Table 5.26 Register 5 - Auto Negotiation Link Partner Ability42Table 5.27 Register 6 - Auto Negotiation Expansion43Table 5.28 Register 16 - Silicon Revision43Table 5.29 Register 17 - Mode Control/Status43Table 5.30 Register 18 - Special Modes44Table 5.31 Register 26 - Symbol Error Counter44Table 5.32 Register 27 - Special Control/Status Indications45Table 5.33 Register 28 - Special Internal Testability Controls45Table 5.34 Register 29 - Interrupt Source Flags45Table 5.35 Register 30 - Interrupt Mask46Table 5.36 Register 31 - PHY Special Control/Status465.2 Interrupt Management475.2.1 Primary Interrupt System47Table 5.37 Interrupt Management Table475.2.2 Alternate Interrupt System48Table 5.38 Alternative Interrupt System Management Table485.3 Miscellaneous Functions485.3.1 Carrier Sense485.3.2 Collision Detect495.3.3 Isolate Mode495.3.4 Link Integrity Test495.3.5 Power-Down modes495.3.6 Reset505.3.7 LED Description505.3.8 Loopback Operation50Figure 5.1 Near-end Loopback Block Diagram51Figure 5.2 Far Loopback Block Diagram51Figure 5.3 Connector Loopback Block Diagram525.3.9 Configuration Signals52Table 5.39 Pin Names for Address Bits52Table 5.40 MODE[2:0] Bus53Table 5.41 Pin Names for Mode Bits53Chapter 6 AC Electrical Characteristics556.1 Serial Management Interface (SMI) Timing55Figure 6.1 SMI Timing Diagram55Table 6.1 SMI Timing Values556.2 MII 10/100Base-TX/RX Timings566.2.1 MII 100Base-T TX/RX Timings56Figure 6.2 100M MII Receive Timing Diagram56Table 6.2 100M MII Receive Timing Values56Figure 6.3 100M MII Transmit Timing Diagram57Table 6.3 100M MII Transmit Timing Values576.2.2 MII 10Base-T TX/RX Timings58Figure 6.4 10M MII Receive Timing Diagram58Table 6.4 10M MII Receive Timing Values58Figure 6.5 10M MII Transmit Timing Diagrams59Table 6.5 10M MII Transmit Timing Values596.3 RMII 10/100Base-TX/RX Timings (50MHz REF_CLK IN)606.3.1 RMII 100Base-T TX/RX Timings (50MHz REF_CLK IN)60Figure 6.6 100M RMII Receive Timing Diagram (50MHz REF_CLK IN)60Table 6.6 100M RMII Receive Timing Values (50MHz REF_CLK IN)60Figure 6.7 100M RMII Transmit Timing Diagram (50MHz REF_CLK IN)61Table 6.7 100M RMII Transmit Timing Values (50MHz REF_CLK IN)616.3.2 RMII 10Base-T TX/RX Timings (50MHz REF_CLK IN)62Figure 6.8 10M RMII Receive Timing Diagram (50MHz REF_CLK IN)62Table 6.8 10M RMII Receive Timing Values (50MHz REF_CLK IN)62Figure 6.9 10M RMII Transmit Timing Diagram (50MHz REF_CLK IN)63Table 6.9 10M RMII Transmit Timing Values (50MHz REF_CLK IN)636.4 RMII CLKIN Requirements64Table 6.10 RMII CLKIN (REF_CLK) Timing Values646.5 Reset Timing64Figure 6.10 Reset Timing Diagram64Table 6.11 Reset Timing Values646.6 Clock Circuit65Table 6.12 LAN8710/LAN8710i Crystal Specifications65Chapter 7 DC Electrical Characteristics667.1 DC Characteristics667.1.1 Maximum Guaranteed Ratings66Table 7.1 Maximum Conditions66Table 7.2 ESD and LATCH-UP Performance667.1.2 Operating Conditions67Table 7.3 Recommended Operating Conditions677.1.3 Power Consumption68Table 7.4 Power Consumption Device Only687.1.4 DC Characteristics - Input and Output Buffers69Table 7.5 MII Bus Interface Signals69Table 7.6 LAN Interface Signals70Table 7.7 LED Signals70Table 7.8 Configuration Inputs70Table 7.9 General Signals70Table 7.10 Internal Pull-Up / Pull-Down Configurations71Table 7.11 100Base-TX Transceiver Characteristics71Table 7.12 10BASE-T Transceiver Characteristics72Chapter 8 Application Notes738.1 Application Diagram738.1.1 MII Diagram73Figure 8.1 Simplified Application Diagram738.1.2 Power Supply Diagram74Figure 8.2 High-Level System Diagram for Power748.1.3 Twisted-Pair Interface Diagram74Figure 8.4 Copper Interface Diagram748.2 Magnetics Selection75Chapter 9 Package Outline76Figure 9.1 LAN8710/LAN8710i-EZK 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free)76Table 9.1 32 Terminal QFN Package Parameters76Figure 9.1 QFN, 5x5 Taping Dimensions and Part Orientation77Figure 9.2 Reel Dimensions for 12mm Carrier Tape78Figure 9.3 Tape Length and Part Quantity79Размер: 1,1 МБСтраницы: 79Язык: EnglishПросмотреть