Emerson 752I 用户手册

 Signal Control

752i User’s Manual

Figure 13-1:

The Katana

752i supports control signals that allow a PTMC site to master the CT clocks 

and/or data. The control registers are located in the Hot Swap Logic (HSL) programmable 
logic device (PLD) at hex address F821,0003

16

. The 750GL processor can access these reg-

isters. The following table summarizes the direction control registers:

Table 13-1:

NETREF1_DIR

0

1

Controls direction of NETREF (on J4):
1=Katana

is NETREFx slave 

(input)

0=Katana

752i is NETREFx master 

(output)

These bits are not used.

NETREF2_DIR

1

1

C8_FRAME_A_TERM

2

1

Controls termination of FRAME and C8 data signals (on J4):
1=Katana

752i is not clock master (33 ohm series 

termination)

0=Katana

752i is clock master (no series termination)

Controls termination on clock signals:
1=33-ohm series termination present
0=no termination

C8_FRAME_B_TERM

3

1

Primary

Master

Secondary

Master

Bits

Derived

Source

Slave

Digital

Trunk

Card

Slave

Digital

Trunk

Card